Clock Source - ST STM32F423 Reference Manual

Basic timers (TIM6/7)
Figure 212. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
20.3.3

Clock source

The counter clock is provided by the Internal clock (CK_INT) source.
The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual
control bits and can be changed only by software (except for UG that remains cleared
automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal
clock CK_INT.
Figure 213
without prescaler.
648/1324
shows the behavior of the control circuit and the upcounter in normal mode,
RM0430 Rev 8
preloaded)
RM0430