Clock Source; Figure 195. Control Circuit In Normal Mode, Internal Clock Divided By 1 - ST STM32F100 Series Reference Manual

Basic timers (TIM6 and TIM7)
Figure 194. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
Update interrupt flag (UIF)
Auto-reload preload register
Auto-reload shadow register
16.3.3

Clock source

The counter clock is provided by the Internal clock (CK_INT) source.
The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual
control bits and can be changed only by software (except for UG that remains cleared
automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal
clock CK_INT.
Figure 195
without prescaler.

Figure 195. Control circuit in normal mode, internal clock divided by 1

CEN=CNT_EN
Counter clock = CK_CNT = CK_PSC
Counter register
462/709
CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Write a new value in TIMx_ARR
shows the behavior of the control circuit and the upcounter in normal mode,
Internal clock
UG
CNT_INIT
31
preloaded)
F0 F1 F2 F3 F4 F5 00
F5
F5
3 2 33 34 35 36
RM0041 Rev 6
01 02 03 04 05 06 07
36
36
00 01 02 03 04 05
RM0041
MSv37304V1
06 07
MS31085V2