Figure 4. Select The Clock Source; Figure 5. File Generation Error - ST STM32F0 Series Application Note

AN4055
Note: In this product PCLK1 and PCLK2 share the some clock signal, so APB1 prescaler should
always equal APB2 prescaler.
6. If the I2S clock is needed, select the frame width (16 or 32 bits).
7. Specify if the master clock is enabled or disabled (Select ON/OFF from the list box).
8. Select the Frequency from the list box. The Fs value can be 192 kHz, 96 kHz, 48 kHz,
44.1 kHz, 32 kHz, 22.05 kHz, 16 kHz, 11.025 kHz, or 8 kHz.
9. Click the RUN button.
If more than one clock source is possible, a message box displays the clock sources
that can be selected (see
the HSI or HSE).
Figure 4.
10. Click the Generate button to automatically generate system_stm32f0xx.c file.
The system_stm32f0xx.c file is generated in the same location as the clock tool.
Display the file to verify the value of the system clock, SystemCoreClock, and the
values of HCLK, PCLK1, PCLK2, Flash access mode, and other parameters which are
defined in the SetSysClock function.
If the file is not generated, an error message is displayed as shown
Figure 5.
11. The system_stm32f0xx.c file must be added to the working project to be built.
Figure
Select the clock source
File generation error
Doc ID 022837 Rev 1
4). Choose HSE, HSI or PLL (which are sourced by
Tutorials
Figure 5.
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