ST STM32G4 Series Reference Manual page 2024
Advanced arm-based 32-bit mcus
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- Reference manual (2126 pages) ,
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USB Type-C™ / USB Power Delivery interface (UCPD)
Bits 15:11 TRANSWIN[4:0]:
This field is modified by software.
This register is static and as such can only be updated when UCPDEN=0.
The number of cycles (minus 1) of the half bit clock (see HBITCLKDIV) to achieve a legal
tTransitionWindow (set according to IP clock to define an interval of between 12 and 20 us)
0x0: Not supported
0x9: Divide by 10 (recommended value)
0x1F: Divide by 32 (maximum division)
Bits 10:6 IFRGAP[4:0]:
This field is modified by software.
This register is static and as such can only be updated when UCPDEN=0.
Clock divider value is used to generate Interframe gap (tInterframeGap) hardware timer
This bit contains the definition of the clock divider (minus 1) in order to generate tInterframeGap
from the IP clock.
0x0: Not supported
0xD: Divide by 14 (may be useful if Tx clock is below nominal value in USB PD 2.0
specification)
0xE: Divide by 15 (ideal value if Tx clock is exactly nominal value in USB PD 2.0
specification)
0xF: Divide by 16 (may be useful if Tx clock is above nominal value in USB PD 2.0
specification)
0x1F: Divide by 32 (maximum division)
Bits 5:0 HBITCLKDIV[5:0]:
This field is modified by software.
This register is static and as such can only be updated when UCPDEN=0.
Clock divider values is used to generate a half-bit clock.
This register contains the number of cycles (minus one) at the IP for a half bit clock e.g.
program 3 for a bit clock that takes 8 cycles of the IP clock "UCPD_CLK".
0x0: Divide by 1 to produce HBITCLK
0x1A: Divide by 27 to produce HBITCLK (recommended value)
0x3F: Divide by 63 to produce HBITCLK
45.7.2
UCPD configuration register 2 (UCPD_CFG2)
Address offset: 0x004
Reset value: 0x0000 0000
This register is used for the configuration of Rx signal filtering in the UCPD.
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