ST STM32G4 Series Reference Manual page 2023

RM0440
Bit 31 UCPDEN: USB Power Delivery Block Enable
This field is modified by software.
It shall be used to enable the peripheral. When disabled, the block is not functional, no received
information on CC will be seen or acted upon. After enabling this bit the block is functional and
receive logic will immediately start detection on the CC input. When disabled, the IP will
terminate any ongoing activity instantly. This behaviour is important, notably, for proper
termination of "Carrier Mode 2" transmission.
0: Disable UCPD, the kernel behaves as if all control registers are in the reset state (in fact 0)
1: Enable UCPD. Note that each register including control bits (this done not include the
configuration registers) all of them should be re-written to their desired values.
Bit 30 RXDMAEN: DMA reception requests enable
This field is modified by software.
This register is static and as such can only be updated when UCPDEN=0.
0: DMA mode disabled for reception
1: DMA mode enabled for reception
Bit 29 TXDMAEN: DMA reception requests enable
This field is modified by software.
This register is static and as such can only be updated when UCPDEN=0.
0: DMA mode disabled for transmission
1: DMA mode enabled for transmission
Bits 28:20 RXORDSETEN[8:0]: Receiver ordered set detection enable
This field is modified by software.
This register is static and as such can only be updated when UCPDEN=0.
Determines the types of ordered sets that the receiver shall detect.
0bxxxxxxxx1: SOP detect enabled
0bxxxxxxx1x: SOP' detect enabled
0bxxxxxx1xx: SOP'' detect enabled
0bxxxxx1xxx: Hard Reset detect enabled
0bxxxx1xxxx: Cable Detect reset enabled
0bxxx1xxxxx: SOP'_Debug enabled
0bxx1xxxxxx: SOP''_Debug enabled
0bx1xxxxxxx: SOP extension#1 enabled
0b1xxxxxxxx: SOP extension#2 enabled
Bits 19:17 PSC_USBPDCLK[2:0]: Pre-scaler for UCPD_CLK. Incoming kernel clock will first be pre-
scaled according to this setting before any other divisions (e.g. those done by TRANSWIN ;
IFRGAP; HBITCLKDIV) This division would be useful for cases where incoming clock is above
18 MHz (and could also be considered in the range of 12-18 MHz, where a division by 2 would
give 6-9 MHz)
This field is modified by software.
This register is static and as such can only be updated when UCPDEN=0.
0x0: Bypass pre-scaling / divide by 1
0x1: Pre-scale clock by dividing by 2
0x2: Pre-scale clock by dividing by 4
0x3: Pre-scale clock by dividing by 8
0x4: Pre-scale clock by dividing by 16
Bit 16 Reserved
USB Type-C™ / USB Power Delivery interface (UCPD)
RM0440 Rev 1 2023/2083
2040