ST STM32G4 Series Reference Manual page 2016

USB Type-C™ / USB Power Delivery interface (UCPD)
FRS detection
FRS monitoring is enabled by bit FRSRXEN, and this should only be enabled after the
correct value of PHYCCSEL is written (this is a result of establishing the CC position
dependent on cable orientation).
45.4.9 UCPD DMA Interface
DMA is implemented in the UCPD and when it is enabled the byte-level interrupts to handle
USBPD1_TXDR and USBPD1_RXDR registers (Tx and Rx data register, each one byte)
are no longer needed.
By enabling bits TXDMAEN and/or RXDMAEN, DMA can be activated independently for Tx
and/or Rx functionality.
45.4.10 Wakeup from STOP
For power consumption optimization it is useful to be able to use STOP mode and wait for
events on the CC pins to wake up the MCU to RUN.
In order for this to work, it must be first enabled by writing a 1 to WUPEN.
The events causing the wakeup can be:
• Events on the BMC receiver (RXORDDET ; RXHRSTDET), hardware enable
PHYRXEN
•
Event on the FRS detector (FRSEVT), hardware enable FRSRXEN
•
Events on the Type-C detectors (TYPECEVT1 ; TYPECEVT2), hardware enables
CC1TCDIS; CC2TCDIS
45.4.11 UCPD programming sequences
The following example illustrates the normal use of this UCPD.
–
–
In parallel start two processes:
–
–
Repeat the above forever.
Initialization phase
Use the following sequence for a clean startup:
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–
Type-C state machine handling
For the general application cases of source, sink (and also dual role port which can switch
between those two) the software must implement the relevant USB Type-C state machine.
The basic coding is shown below in
link with
2016/2083
Configure UCPD
Enable UCPD
[On demand from Protocol Layer] Send Tx message
Poll (or wait for interrupt) concerning Rx messages and recover detail to hand off
to Protocol Layer
Prepare all clock divider values initially by writing register UCPD_CFG
Enable the block via UCPDEN
TYPEC_VSTATE_CCx:
Table 419: Coding for ANAMODE, ANASUBMODE and
RM0440 Rev 1
RM0440