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Chapter 8
Random Number Generator
This chapter explains how to program the RNG (Random Number Generator) to create a
random number.
8.1 Overview
The RNG is a digital integrated circuit capable of generating 32-bit random numbers. It is
designed to comply with the FIPS-140 standard for randomness and non-determinism. A
linear feedback shift register (LSFR) and cellular automata shift register (CASR) are
operated in parallel to generate pseudo-random data.
8.2 Functional Description
The RNG consists of six major functional blocks:
• Bus Interface Unit (BIU)
• Linear Feedback Shift Register (LFSR)
• Cellular Automata Shift Register (CASR)
• Clock Controller
• 2 Ring Oscillators
The states of the LFSR and CASR are advanced at unknown frequencies determined by the
two ring oscillator clocks and the clock control. When a read is performed, the oscillator
clocks are halted and a collection of bits from the LFSR and CASR are x'ored together to
obtain the 32-bit random output. The BIU interfaces with the External Bus Interface (EBI)
to allow communication between the EBI and the RNG.
8.3 Typical Operation
A typical procedure for reading random data is as follows. When a given operation calls for
random data, the CPU writes the number of 32-bit random words required to the MPC180E
EBI, specifically to the Output Buffer Count Register (see section 3.3.1.5). The EBI
monitors the ORDY bit in the RNG Status Register (Fig 8-1). This bit signals whether the
random data is ready. Once the ORDY bit goes low, the EBI reads the 32-bit word from the
RNG Random Output Register (Table 8-1) and writes it to the MPC180E Output FIFO,
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Chapter 8. Random Number Generator
8-1
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