Idma Programming Examples; Peripheral-To-Memory Mode (60X Bus To Local Bus)Ñidma2 - Motorola MPC8260 PowerQUICC II User Manual

Table 18-14 describes parallel I/O register programming for port D (optional).
Table 18-14. Parallel I/O Register ProgrammingÑPort D
Channel Signal
IDMA1 DACK1 (O)
DONE1 (I/O)

18.12 IDMA Programming Examples

These programming examples demonstrate the use of most of the different modes and
conÞgurations of the IDMA channels.
18.12.1 Peripheral-to-Memory Mode (60x Bus to Local Bus)ÑIDMA2
In the example in Table 18-15, the IDMA2 channel reads 8 bytes per DREQ assertion from
a Þxed address peripheral located on the 60x bus into the internal buffer. When there is
enough data in the internal buffer, it writes one burst to the memory located on the local
bus. The internal buffer size is set to 64 bytes to handle maximum transfer of a single burst.
The IDMA2 channel asserts DONE on the last read transfer of the last BD to notify the
peripheral that there is no data left to transfer.
Table 18-15. Example: Peripheral-to-Memory ModeÑIDMA2
Important Init Values
DCM(FB) = 0
DCM(LP) = 0
DCM(DMA_WRAP) =
000
DCM(ERM) = 1
DCM(DT) = 0
DCM(S/D) = 10
DCM(SINC) = 0
DCM(DINC) = 1
DPR_BUF = 0x0DC0
IBASE = IBDPTR =
0x0030
STS = 8 (0x0008)
DTS = 32 (0x0020)
Every BD(SDTB) = 1
Every BD(DDTB) = 0
MOTOROLA
Pin PPARD
PD[6] 1
PD[5] 1
Not in ßy-by mode.
Transfers to memory have middle CPM request priority. The destination bus is not overloaded.
The internal buffer is 64 bytes long to support 32-byte transfers to memory on the destination
bus (one 60x burst) on steady-state of work.
Transfers from peripheral are initiated by DREQ. DONE assertion is supported.
Assertion of DONE by the peripheral causes the transfer to be terminated, after writing all the
data in the internal buffer to memory, interrupt EDN is set to the core, IDMA channel is
stopped. additional DREQ assertions are ignored, until
Peripheral-to-memory mode. DONE DREQ and DACK are connected to the peripheral.
The peripheral address are not incremented after transfers, Þxed location.
The memory address is incremented after every transfer.
Initiated to address aligned to 64 (bit[5Ð0]= 00000).
The current BD pointer is set to the BD table base address (aligned 16 -bits[3Ð0] = 0).
Transfers from peripheral are always single 8-byte accesses.
Transfers to memory are 32 bytes long (60x bursts) on steady-state of work.
Peripheral is on the 60x bus.
Memory is on the local bus.
Chapter 18. SDMA Channels and IDMA Emulation
Part IV. Communications Processor Module
PDIRD PODRD PSORD
1 0
0 1
Description
START
Default
1 Ñ
1 VDD
_ command is issued.
IDMA
18-29