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4.5.3 OSI Exception (Ox00300)
A OSI exception occurs when no higher priority exception exists and an error condition
related to a data memory access occurs. The OSI exception is implemented as it is defined
in the PowerPC architecture (OEA). In case of a TLB miss for a load, store, or cache
operation, a OSI exception is taken if the resulting hardware table search causes a page
fault.
On the MPC750, a OSI exception is taken when a load or store is attempted to a direct-store
segment (SR[T]
=
1).
In the MPC750, a floating-point load or store to a direct-store
segment causes a OSI exception rather than an alignment exception, as specified by the
PowerPC architecture.
The MPC750 also implements the data address breakpoint facility, which is defined as
optional in the PowerPC architecture and is supported by the optional data address
breakpoint register (OABR). Although the architecture does not strictly prescribe how this
facility must be implemented, the MPC750 follows the recommendations provided by the
architecture and described in the Chapter 2, "Programming Model," and Chapter 6
"Exceptions," in The Programming Environments Manual.
4.5.4 lSI Exception (Ox00400)
An lSI exception occurs when no higher priority exception exists and an attempt to fetch
the next instruction fails. This exception is implemented as it is defined by the PowerPC
architecture (OEA), and is taken for the following conditions:
•
The effective address cannot be translated.
• The fetch access is to a no-execute segment (SR[N]
=
1).
•
The fetch access is to guarded storage and MSR[IR]
=
1.
•
The fetch access is to a segment for which SR[T] is set.
•
The fetch access violates memory protection.
When an lSI exception is taken, instruction fetching resumes at offset Ox00400 from the
physical base address indicated by MSR[IP].
4.5.5 External Interrupt Exception (Ox00500)
An external interrupt is signaled to the processor by the assertion of the external interrupt
signal (INT). The INT signal is expected to remain asserted until the MPC750 takes the
external interrupt exception. If INT is negated early, recognition of the interrupt request is
. not guaranteed. After the MPC750 begins execution of the external interrupt handler, the
system can safely negate the INT. When the MPC750 detects assertion of INT, it stops
dispatching and waits for all pending instructions to complete. This allows any instructions
in progress that need to take an exception to do so before the external interrupt is taken.
After all instructions have vacated the completion buffer, the MPC750 takes the external
interrupt exception as defined in the PowerPC architecture (OEA).
Chapter 4. Exceptions
4-17
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