Interrupt Mask Register; Table 9-5 Interrupt Mask Register Description - Motorola MC68VZ328 User Manual

Programming Model
9.6.3

Interrupt Mask Register

The interrupt mask register (IMR) can mask out a particular interrupt if the corresponding bit for the
interrupt is set. There is one control bit for each interrupt source. When an interrupt is masked, the interrupt
controller will not generate an interrupt request to the CPU, but its status can still be observed in the
interrupt pending register. At reset, all the interrupts are masked and all the bits in this register are set to 1.
IMR
BIT
30 29
31
TYPE
0 0 0
RESET
BIT
14 13
15
MP
WM
2
TYPE rw
0 0 1
RESET
Name
Reserved Reserved
Bits 31–24
MEMIQ Mask Emulator Interrupt—When set, this bit indicates that
Bit 23 the EMUIRQ pin and in-circuit emulation breakpoint interrupt
functions are masked. It is set to 1 after reset. These inter-
rupts are level 7 interrupts to the CPU.
MRTI Timer for Real-Time Clock—When set, this bit indicates
Bit 22 that the real-time interrupt timer is masked. It is set to 1 after
reset.
MSPI1 Mask SPI1 Interrupt—When set, this bit indicates that the
Bit 21 SPI 1 interrupt is masked. It is set to 1 after reset.
MIRQ5 Mask IRQ5 Interrupt—When set, this bit indicates that IRQ5
Bit 20 is masked. It is set to 1 after reset.
MIRQ6 Mask IRQ6 Interrupt—When set, this bit indicates that IRQ6
Bit 19 is masked. It is set to 1 after reset.
MIRQ3 Mask IRQ3 Interrupt—When set, this bit indicates that IRQ3
Bit 18 is masked. It is set to 1 after reset.
9-10
Interrupt Mask Register
28 27 26 25
0 0 0 0
12 11 10 9
MU MI MI MI
AR NT NT NT
T2 3 2 1
rw rw rw rw
1 1 1 1
Table 9-5. Interrupt Mask Register Description
Description
MC68VZ328 User's Manual
24 23 22 21
ME MR MS
MIQ TI PI1
rw rw rw
0 1 1 1
0x00FF
8 7 6 5
MI MP MT
MK
NT WM MR
B
0 1 2
rw rw rw rw
1 1 1 1
0xFFFF
These bits are reserved and should
be set to 0.
0 = Enable EMUIRQ interrupt
1 = Mask EMUIRQ interrupt
0 = Enable real-time interrupt timer
1 = Masked real-time interrupt
0 = Enable SPI 1 interrupt.
1 = Mask SPI 1 interrupt.
0 = Enable IRQ5 interrupt.
1 = Mask IRQ5 interrupt.
0 = Enable IRQ6 interrupt.
1 = Mask IRQ6 interrupt.
0 = Enable IRQ3 interrupt.
1 = Mask IRQ3 interrupt.
0x(FF)FFF304
20 19 18 17
MIR MIR MIR MIR
Q5 Q6 Q3 Q2
rw rw rw rw
1 1 1 1
4 3 2 1
MU MT
MR MW
AR MR
TC DT
T1 1
rw rw rw rw
1 1 1 1
Settings
interrupt.
timer interrupt.
BIT
16
MIR
Q1
rw
1
BIT
0
MS
PI2
rw
1