Lcd Sram/Rom Dma Cycle 16-Bit Mode Access (1 Wait State); Figure 19-10 Lcd Sram/Rom Dma Cycle 16-Bit Mode Access Timing Diagram; Table 19-11 Dram Hidden Refresh Cycle (Low-Power Mode) Timing Parameters - Motorola MC68VZ328 User Manual

Table 19-11. DRAM Hidden Refresh Cycle (Low-Power Mode) Timing Parameters
Number
1 CASx pulse width
2 RASx pulse width
3 CASx asserted to RASx asserted
4 CASx negated to RASx negated
5 Refresh cycle (using 32.768 KHz crystal)
5 Refresh cycle (using 38.400 KHz crystal)
6 DWE negated before CASx asserted
Note: RASx stands for RAS0 and RAS1. CASx stands for CAS0 and CAS1.
19.3.10 LCD SRAM/ROM DMA Cycle 16-Bit Mode Access (1
Wait State)
Figure 19-10 shows the LCD SRAM/ROM DMA cycle timing diagram for 16-bit access (1 wait state).
Note that WS is the number of wait states in the current memory access cycle. The signal values and units
of measure for this figure are found in Table 19-12 on page 19-14. Detailed information about the
operation of individual signals can be found in Chapter 7, "DRAM Controller," and Chapter 8, "LCD
Controller."
CLKO
A[31:0]
CSx
UWE/LWE
OE
D[15:0]
Figure 19-10. LCD SRAM/ROM DMA Cycle 16-Bit Mode Access Timing Diagram
Characteristic
2+1WS 2+1WS
4
Addr
5
1
2
3
Electrical Characteristics
AC Electrical Characteristics
(3.0 ± 0.3) V
Minimum
120
120
30
30
15
13
58
2+1WS
Addr+1 Addr+2
Unit
Maximum
— ns
— ns
— ns
— ns
— us
— us
— ns
Addr+n
19-13