Ecc/Parity Mode - Motorola MPC8260 PowerQUICC II User Manual

Part III. The Hardware Interface
MPC8260
CPU_BR, CPU_BG, CPU_DBG
TS, TT[0:4], TBST, TSIZ[1Ð3]
CI, GBL, TA, DBB, TEA
AACK, ARTRY
Memory Controller
Figure 11-2. External L2 Cache in Write-Through Mode

11.1.3 ECC/Parity Mode

ECC/parity mode is a subset of write-through mode with some connection changes that
allow the L2 cache to support ECC or Parity. The connection changes are:
¥ The MPC8260Õs DP[0:7] signals are connected to the L2 cacheÕs DP[0:7] signals.
¥ The L2Õs TSIZ[0:2] signals are pulled down to always indicate 8-byte transaction
size.
¥ The L2Õs A[29:31] signals are pulled down.
11-4
(pull up)
BR
BG
DBG
TSIZ[0]
(pull down)
L2_HIT
A[0Ð31]
D[0Ð63]
SDRAM Main Memory
MPC8260 PowerQUICC II UserÕs Manual
(pull up)
L2BR
L2BG
L2DBG
CPU_BR,CPU_BG,CPU_DBG
TS, TT[0Ð4], TBST, TSIZ[0Ð2]
CI, GBL, TA, DBB, TEA
AACK, ARTRY
WT
(pull down)
L2_CLAIM
A[0Ð31]
D[0Ð63]
Latch
MUX
MPC2605
I/O Devices
MOTOROLA