Memory Interface - Motorola MC68020 User Manual

12.5-MHz
OSCILLATOR
50-MHz
OSCILLATOR

9.5 MEMORY INTERFACE

The MC68020/EC020 is capable of running an external bus cycle in a minimum of three
clocks (refer to Section 5 Bus Operation). The MC68020/EC020 runs an asynchronous
bus cycle, terminated by the DSACK1/DSACK0 signals, and has a minimum duration of
three controller clock periods in which up to four bytes (32 bits) are transferred.
During read operations, the MC68020/EC020 latches data on the last falling clock edge of
the bus cycle, one-half clock before the bus cycle ends. Latching data here, instead of the
next rising clock edge, helps to avoid data bus contention with the next bus cycle and
allows the MC68020/EC020 to receive the data into its execution unit sooner for a net
performance increase.
Write operations also use this data bus timing to allow data hold times from the negating
strobes and to avoid any bus contention with the following bus cycle. This
MC68020/EC020 characteristic allows the system to be designed with a minimum of bus
buffers and latches.
One benefit of the MC68020/EC020 on-chip instruction cache is that the effect of external
wait states on performance is lessened because the caches are always accessed in fewer
than "no wait states," regardless of the external memory configuration.
MOTOROLA
MC88916
CLOCK
(25 MHz)
Figure 9-7. High-Resolution Clock Controller
MC74F803
BUS CLOCKS
(25 MHz)
Figure 9-8. Alternate Clock Solution
M68020 USER'S MANUAL
CONTROLLER
CLOCK (25 MHz)
12.5 MHz
CLOCK
(50 MHz)
2
BUS CLOCKS
(25 MHz)
CONTROLLER
CLOCK (25 MHz)
2
CLOCK
(25 MHz)
MC68020/EC020
25 MHz
MC68020/EC020
25 MHz
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