Hardware Implementation-Dependent Register 0 - Motorola MPC750 User Manual

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Address
29 30 31
Figure 2-2. Instruction Address Breakpoint Register
The IABR bits are described in Table 2-3.
Table 2-3. Instruction Address Breakpoint Register Bit Settings
Bits
Name
Description
0-29 Address Word address to be compared
30
BE
Breakpoint enabled. Setting this bit indicates that breakpoint checking is to be done.
31
TE
Translation enabled. An IABR match is signaled if this bit matches MSR[IR].
2.1.2.2 Hardware Implementation-Dependent Register 0
The hardware implementation-dependent register 0 (HIDO) controls the state of several
functions within the MPC750. The HIDO register is shown in Figure 2-3.
o
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Figure 2-3. Hardware Implementation-Dependent Register 0
(HI DO)
The HIDO bits are described in Table 2-4.
Table 2-4. HIDO Bit Functions
Bit
Name
Function
0
EMCP
Enable Mep. The primary purpose of this bit is to mask out further machine check exceptions
caused by assertion of Mep, similar to how MSR[EE] can mask external interrupts.
0 Masks Mep. Asserting MCP does not generate a machine check exception or a checkstop.
1 Asserting Mep causes checkstop if MSR[ME]
=
0 or a machine check exception if ME
=
1.
1
DBP
Enable/disable 60x bus address and data parity generation.
0 If the system does not use address or data parity and the respective parity checking is disabled
(HIDO[EBA] or HIDO[EBD]
=
0), input receivers for those signals are disabled, require no pull-up
resistors, and thus should be left unconnected. If all parity generation is disabled, all parity
checking should also be disabled and parity signals need not be connected.
1 Parity generation is enabled.
2
EBA
Enable/disable 60x bus address parity checking
0 Prevents address parity checking.
1 Allows a address parity error to cause a checkstop if MSR[ME]
=
0 or a machine check
exception if MSR[ME]
=
1.
EBA and EBD allow the processor to operate with memory subsystems that do not generate parity.
Chapter 2. MPC750 Processor Programming Model
2-9

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