Dram Design Techniques; Extended Data Output Ram (Edo Ram) - Intel Embedded Intel486 Hardware Reference Manual

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EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
9.7

DRAM DESIGN TECHNIQUES

An efficient DRAM memory design is needed for a high-performance Intel486 processor system.
For some applications, the principle of locality will not be as applicable. A common technique of
improving performance with DRAMs uses the commonly seen attribute of locality of reference
in programs. This works well with the fast access modes offered by DRAMs that use the same
row address. As a result, system performance is more dependent upon DRAM latency.
Normally, a DRAM access is made by first asserting RAS# (Row Address Strobe) to latch the
presented row address into the DRAM device. As the DRAM devices have multiplexed address
pins, the address must then be externally switched to present the column address. Finally, the
CAS# (Column Address Strobe) is asserted to latch the column address and enable the DRAM
output buffers. Refer to
accessing.
The simplest DRAM design offers a fixed number of wait states for each access. As an example,
a system could be designed such that all DRAM accesses occur in six clocks. However, many
DRAMs offer special modes of operation based on the policy of updating the row address which
have higher performance. Some of these modes and their impact on performance are discussed
below.
9.8

EXTENDED DATA OUTPUT RAM (EDO RAM)

In Extended Data Output (EDO) RAM designs, a set of gates latch the output data until the CPU
reads the data. This is important for high-speed designs because EDO RAM handles sequential
reads better than Fast Page Mode (FPM) RAM. Extended Data-Out page mode read accesses are
similar to FPM read accesses, except that when CAS is driven high, the data outputs are not dis-
abled, and the data latch is used to guarantee that the valid data is held until CAS goes low again.
With EDO RAM, the data latch is controlled during page-mode accesses by CAS. Data is then
captured in the latch as a result of CAS going high. A new address can then be applied, and new
data accessed, without corrupting the output data from the previous access.
The advantage of an EDO RAM design is that EDO memory has a shorter Page Mode cycle than
standard FPM DRAM. Since EDO RAM does not turn the data off by the rising edge of CAS, the
data is available longer, enabling the system to read the output data while readying for the next
cycle, thus saving one clock cycle for every page access. By eliminating data cycles, EDO mem-
ory designs offer an increased peak bandwidth and simplified constraints on access timing, which
increase memory performance.
9.8.1
Interleaving
A more complicated DRAM design technique is called interleaving. Interleaving is possible
when more than one memory bank is used. Effective implementation of interleaving brings high-
er performance to a design.
detail.
Interleaving controls each bank separately. As an access is occurring, the other (non-accessed)
banks are being readied for their next access. Interleaving can help provide fast burst accesses for
designs. In addition, another use of interleaving is to hide the RAS# precharge time, which is in-
curred on page misses for paged memory designs. As the number of banks is increased, the
9-14
Chapter 5, "Memory Subsystem Design"
Chapter 5, "Memory Subsystem Design"
for specific details of memory
discusses design issues in

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