Big-Endian Support; Indivisible Operations; Processor Locks - Intel 460GX Software Developer’s Manual

System Architecture
Arbitration for Outbound Transactions
The WXB relies heavily on the PCIset core and the PCI Specification regarding transaction
ordering for dealing with starvation on outbound transactions. Once the WXB has won PCI
arbitration for an outbound transaction, the WXB will initiate the request at the top of the
Outbound Transaction Queue (OTQ) unless there is a read within the Outbound Read Request
FIFO (ORRF). In this case, if the read at the top of the ORRF has already received some data, and
the transaction at the top of the OTQ is a read, it will be moved behind the read in the ORRF. The
read at the head of the ORRF will then be initiated on the PCI bus. The read at the head of the
ORRF will be moved to the back if it hasn't already received some data. If, however, the
transaction at the top of the OTQ is a write, then the arbitration policy will be to choose, on a
round-robin basis, between the read at the head of the ORRF and the write. The write will attempt
to burst to the end of a cache line; if there are no reads in the ORRF at the end of the cache line
burst, the write will continue to burst to the end of the next cache line unless the MLT causes the
WXB to disconnect.
The IHPC will also participate in arbitration with the purpose of idling the PCI bus. When the
IHPC has won grant, and FRAME# has deasserted, there will be moments of inactivity as the IHPC
alters the state of various external signal and power control registers for one or more PCI slots.
3.5

Big-endian Support

The Itanium processor supports both little-endian and big-endian accesses. The chipset does not
need to know which mode the processor is in. The chipset provides data in the same manner in both
cases. There is no indication on the system bus which mode the processor is using.
3.6

Indivisible Operations

3.6.1

Processor Locks

The 460GX chipset supports locks on the system bus, done by the processor. These locked
transactions are either a series of atomic Read-Write or Read-Read-Write-Write transactions. They
may be targeted to I/O devices or to SDRAM. See 'Transactions' Chapter for the flow for locks.
During the sequence, the system bus is locked and no other traffic can occur on that bus. Traffic
may be flowing throughout the rest of the system, such as AGP to memory or transactions that stay
within the non-locked PCI buses.
The 460GX chipset does not support locks that cross device boundaries. In other words, if the first
read in a locked sequence targets device X, then the remaining transactions in the lock (either R-W-
W or W) must also target device X. The only exception to this rule is when device firmware has
been "in-line shadowed" using the MAR registers. In this case the Read(s) in a locked sequence
can be mapped to the compatibility PCI bus, and the Writes(s) could be mapped to memory. When
a MAR has been mapped to write protect memory, a locked sequence to that MAR region is
completely redirected to PCI, in order to avoid the resource allocation problems associated with
crossing memory/PCI device boundaries. The 460GX chipset does not provide any special checks
to detect locks that cross device boundaries outside of the MARs. If software attempts to establish
such a lock, indeterminate results will occur: either the lock will appear to work, even thought the
access was not performed atomically, or a deadlock will result.
3-4 Intel® 460GX Chipset Software Developer's Manual