Intel Xeon Manuals

Manuals and User Guides for Intel Xeon. We have 6 Intel Xeon manuals available for free PDF download: Design Manual, Datasheet, Specification, User Manual, Manuallines

Intel Xeon Design Manual (305 pages)

Processor with 512 KB L2 Cache and Intel E7500 Chipset Platform

Brand: Intel | Category: Processor | Size: 4 MB

Table of Contents
3
Revision History
14
Introduction

15
Component Quadrant Layout

25
Platform Stack-Up and Component Placement Overview

31
Platform Clock Routing Guidelines

35
- CK408B Clock Groups
  35
- Platform System Clock-Reference
  36
- Intel® E7500 Chipset-Based System Clocking Diagram
  37
- Clock Groups
  38
  - HOST_CLK Clock Group
    38
    
    HOST_CLK Clock Topology
    38
- Source Shunt Termination
  38
- HOST_CLK[1:0]# Routing Guidelines
  39
- Clock Skew as Measured from Agent to Agent
  40
- Trace Spacing for HOST_CLK Clocks
  40
  - HOST_CLK General Routing Guidelines
    41
  - CK408 Vs. CK408B Requirement
    41
- Stuffing Options for CK408 and CK408B
  41
  - CLK66 Clock Group
    42
- Topology for CLK66
  42
- CLK66 Routing Guidelines
  42
  - CLK66 Skew Requirements
    43
- Clock Skew Requirements
  43
- Example of Adding a Single Connector
  44
- Example of Adding Two Connectors And/Or a Riser
  44
  - CLK33_ICH3-S Clock
    45
- Topology for CLK33_ICH3-S
  45
- CLK33_ICH3-S Routing Guidelines
  45
  - CLK33 Clock Group
    46
- Topology for CLK33 to PCI Device down
  46
- CLK33 Routing Guidelines for PCI Device down
  46
- Topology for CLK33 to PCI Slot
  47
- CLK33 Routing Guidelines for PCI Slot
  47
  - CLK14 Clock Group
    48
- Topology for CLK14
  48
- CLK14 Routing Guidelines
  48
  - USBCLK Clock Group
    49
- Topology for USB_CLK
  49
- USBCLK Routing Guidelines
  49
- Clock Driver Decoupling
  50
- Decoupling Capacitors Placement and Connectivity
  50
- Clock Driver Power Delivery
  51
- EMI Constraints
  51
System Bus Routing Guidelines

53
Memory Interface Routing Guidelines

67
Hub Interface

83
82870P2 (P64H2)

93
I/O Controller Hub

119
- IDE Interface
  119
  - Cabling
    119
  - Cable Detection for Ultra ATA/66 and Ultra ATA/100
    120
    
    Combination Host-Side/Device-Side Cable Detection
    120
- Combination Host-Side/Device-Side IDE Cable Detection
  120
  - Primary IDE Connector Requirements
    121
- Connection Requirements for Primary IDE Connector
  121
  - Secondary IDE Connector Requirements
    122
- Connection Requirements for Secondary IDE Connector
  122
- SPKR Pin Consideration
  123
- Pci
  123
- Example Speaker Circuit
  123
- Usb
  124
  - General Routing and Placement
    124
- PCI Bus Layout Example
  124
- Intel ® ICH3-S Smbus/Smlink Interface
  126
- Suggested USB Downstream Power Connection
  126
  - Smbus Design Considerations
    127
  - General Design Note
    127
  - The Unified VCC_CORE Architecture
    127
- Intel® ICH3-S Smbus / Smlink Interface
  127
- Real Time Clock (RTC)
  128
- Unified VCC_3.3 Architecture
  128
- RTCX1 and SUSCLK Relationship
  128
  - RTC External Circuit
    129
- RTC External Circuitry
  129
- RTC Connection When Not Using Internal RTC
  129
  - External Capacitors
    130
  - RTC Layout Considerations
    131
  - RTC External Battery Connection
    131
- A Diode Circuit to Connect RTC External Battery
  131
  - RTC External RTCRST# Circuit
    132
  - VBIAS DC Voltage and Noise Measurements
    132
- RTCRST# External Circuit
  132
  - Susclk
    133
  - RTC-Well Input Strap Requirements
    133
- Internal LAN Layout Guidelines
  133
- Platform LAN Connect
  134
- LAN Design Guide Section Reference
  134
  - LCI (LAN Connect Interface) Guidelines
    135
    
    Bus Topology
    135
- Point-To-Point Interconnect Guideline
  135
  - Signal Routing and Layout
    136
  - Crosstalk Consideration
    136
  - Impedances
    136
  - Line Termination
    136
- LAN_CLK Routing Example
  136
  - General LAN Routing Guidelines and Considerations
    137
    
    General Trace Routing Considerations
    137
- Routing a 90 Degree Bend
  137
  - Trace Geometry and Length
    138
  - Signal Isolation
    138
  - Power and Ground Connections
    138
  - General Power and Ground Plane Consideration
    139
- Ground Plane Separation
  139
  - Board Design
    140
  - Common Physical Layout Issues
    140
  - Intel ® 82562ET/EM Guidelines
    142
    
    Crystals and Oscillators
    142
    
    Guidelines for Intel ® 82562ET/EM Component Placement
    142
    
    Intel ® 82562ET/EM Termination Resistors
    143
  - Critical Dimensions
    143
- Intel ® 82562ET/EM Termination
  143
- Critical Dimensions for Component Placement
  143
  - Terminating Unused Connections
    145
- Termination Plane
  145
Debug Port

147
- Logic Analyzer Interface (LAI)
  147
- Mechanical Considerations
  147
- Electrical Considerations
  147
EMI and Mechanical Design Considerations

149
- Introduction
  149
  - Brief EMI Theory
    149
  - EMI Regulations and Certifications
    150
- EMI Design Considerations
  150
  - Spread Spectrum Clocking (SSC)
    150
    
    Differential Clocking
    151
- Spread Spectrum Modulation Profile
  151
- Impact of Spread Spectrum Clocking on Radiated Emissions
  151
  - PCI Bus Clock Control
    152
- Cancellation of H-Fields through Inverse Currents
  152
  - Heatsink Effects
    153
  - EMI Ground Frames and Faraday Cages
    153
  - EMI Test Capabilities
    154
- Conceptual Processor Ground Frame
  154
  - Retention Mechanism Placement and Keep-Outs
    155
- Retention Mechanism Outline and Ground Pad Detail
  155
- Retention Mechanism Placement and Keep-Out Overview
  156
  - Grounding Techniques
    157
- EMI Ground Size and Location
  157
- Retention Mechanism Ground Ring
  158
Platform Power Delivery Guidelines

159
- Customer Reference Board Power Delivery
  159
- Power Delivery Example
  160
  - Processor Core Voltage
    161
  - 161
    161
  - Vsb
    161
  - Vsb
    162
  - Power Summary
    162
  - Processor Power Distribution Guidelines
    162
    
    Multiple Voltages
    162
    
    Processor Power Requirements
    162
    
    Power Delivery Layout Requirements
    163
    
    Processor Current Requirements
    163
    
    Voltage Tolerance
    163
- Processor Current Step Parameters
  163
  - Voltage Regulator Requirements
    164
    
    Input Voltages and Currents
    165
    
    Power Good Output (PWRGD)
    165
- Power Distribution Block Diagrams for Two-Way System Motherboard
  165
  - Fault Protection
    166
  - VR Module 9.1 Recommendations
    166
  - VR down Recommendations
    167
- VRM VID Routing
  167
- Simplified VRD Circuit Example
  167
- Example Load Line Selection Circuit
  168
  - Voltage Sequencing
    169
- VID Routing
  169
- Power-Up and Power-Down Timing
  170
  - VCCA, VCCIOPLL, and VSSA Filter Specifications
    171
- Processor Filter Topology
  171
- Component Recommendation-Inductor
  171
- Component Recommendation-Capacitor
  171
- Filter Implementation 1: Using Discrete Resistor
  172
- Filter Implementation 2: no Discrete Resistor
  172
  - Processor Decoupling
    173
    
    High-Frequency Decoupling
    173
- Processor High-Frequency Capacitance Recommendations
  173
- Decoupling Example for a Microstrip Baseboard Design
  174
- 1206 Capacitor Pad and Via Layouts
  174
  - Bulk Decoupling
    175
  - Gtlref[3:0]
    175
- GTLREF Divider
  175
- Processor Bulk Capacitance Recommendations
  175
- Suggested GTLREF Generation
  176
  - Component Models
    177
  - Measuring Transients
    177
  - MCH Power Delivery Guidelines
    177
    
    DDR_VTT (1.25 V) Decoupling
    177
    
    VCC_CPU (1.45 V Power Plane)
    177
- Various Component Models Used at Intel (Not Vendor Specifications)
  177
  - DDR (2.5 V Power Plane)
    178
  - Hub Interface (1.2 V Power Plane)
    178
- MCH Decoupling (Backside View)
  178
  - Filter Specifications (1.2V Power Plane)
    179
- Filter Topology for VCCA_1.2 (DDR Interface)
  179
- Filter Topology for VCCAHI_1.2 (HUB Interface)
  179
  - MCH Power Sequencing Requirement
    180
- Filter Topology for VCCAHI_1.2 (System Bus)
  180
- Power Sequencing Requirement for MCH
  180
  - Intel ® ICH3-S Power Delivery Guidelines
    181
    
    V/3.3 V Power Sequencing
    181
- Sample 2.5 V Output Enable Control Logic
  181
  - V/V5REF Sequencing
    182
- Example 1.8 V/3.3 V Power Sequencing Circuit
  182
  - Intel ® ICH3-S Power Rails
    183
  - Intel ® ICH3-S Decoupling Recommendations
    183
- Example 3.3 V/V5REF Sequencing Circuitry
  183
- ICH3-S Power Rail Terminology
  183
- Intel ® ICH3-S Decoupling Recommendations
  184
  - Intel® P64H2 Power Requirements
    185
    
    Intel® P64H2 Current Requirements
    185
    
    Intel® P64H2 Decoupling Requirements
    185
- Intel® P64H2 Max Sustained Currents
  185
- Decoupling Capacitor Recommendations
  185
  - PCIRST# Implementation
    186
  - P64H2 Power Sequencing Requirement
    186
- PCI/PCI-X (VCC_3.3) Capacitor Placement
  186
Schematic Checklist

187
- Processor Schematic Checklist
  187
- MCH Schematic Checklist
  193
- Intel ® ICH3-S Schematic Checklist
  196
- Intel ® 82870P2 P64H2 Schematic Checklist
  204
- Intel ® P64H2 Schematic Checklist
  204
  - CK408 Schematic Checklist
    209
Layout Checklist

211
- Processor Checklist
  211
- Processor Layout Checklist
  211
  - Intel® E7500 MCH Layout Checklist
    213
- MCH Layout Checklist
  213
  - Intel® ICH3-S Layout Checklist
    216
Schematics

221
- Board Connector
  259
- Clock Synthesizer
  287

Intel Xeon Datasheet (96 pages)

Processor with 800 MHz System Bus

Brand: Intel | Category: Processor | Size: 3 MB

Intel Xeon Design Manual (44 pages)

Processor and E7500/E7501 Chipset Compatible Platform. Addendum for Embedded Applications

Brand: Intel | Category: Computer Hardware | Size: 0 MB

Intel Xeon User Manual (38 pages)

Processor with 800 MHz System Bus, Chipset and Development Kit

Brand: Intel | Category: Computer Hardware | Size: 1 MB

Table of Contents
3
Intel ® Xeon™ Processor, Intel
4
Revision History
6
1 Product Overview

7
- Related Documents
  7
- Product Contents
  7
- Products Feature List
  8
- Block Diagram
  9
  - 6300ESB Customer Reference Board Block Diagram
    9
  - E7520 and Intel
    9
  - Placement - Top View
    10
  - DIMM Placement DDR2 400
    11
  - Memory Subsystem
    11
  - Supported DIMM Module Types
    11
- Memory Population Rules and Configurations
  12
- DDR2 400 Memory - DIMM Ordering
  12
2 Platform Management

13
- Power Button
  13
- Soft off
  13
- Sleep States Supported
  13
  - S0 State
    13
  - S1 State
    14
  - S2 State
    14
  - S3 State
    14
  - S4 State
    14
  - S5 State
    15
  - Wake-Up Events
    15
  - Wake-Up from S1 Sleep State
    15
  - Wake-Up from S4 and S5 States
    15
- PCI PM Support
  15
- Platform Management
  15
  - Processor Thermal Management
    16
- System Fan Operation
  16
3 Equipment Required for CRB Usage

17
- Precautions
  17
- Driver and os Requirements
  18
  - Drivers Included on CD
    18
4 Jumpers and Headers

21
5 System Overview

25
- Power Diagrams
  25
- Power Distribution Block Diagram
  25
- Platform Clocking
  26
- Clock Block Diagram
  26
- Platform Resets
  27
- Platform Reset Diagram
  27
- Smbus
  28
- Smbus Block Diagram
  28
- Platform IRQ Routing
  29
- IRQ Routing Diagram
  29
- VRD VID Headers
  30
- Processor VRD Settings
  30
- Miscellaneous Buttons
  32
- Power Buttons
  32
6 Debug Procedure

33

Intel Xeon Specification (56 pages)

Specification Update

Brand: Intel | Category: Computer Hardware | Size: 0 MB

Intel Xeon Manuallines (11 pages)

Processor with 512 KB L2 Cache System Compatibility

Brand: Intel | Category: Computer Hardware | Size: 0 MB

Table of Contents
3
Revision History
4
Introduction
5
- Audience
  5
- References
  5
Compatibility
6
Sm_Vcc
6
603-Pin Socket Pin Definition Changes
6
VCC Power Sequencing
7
Power and Signal Levels
10
VRM 9.0 and VRM 9.1
10
Core Frequency to System Bus Ratio Determination
10

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More Intel Manuals

Intel Xeon Manuals

Intel Xeon Design Manual (305 pages)

Table of Contents

Introduction

Component Quadrant Layout

Platform Stack-Up and Component Placement Overview

Platform Clock Routing Guidelines

System Bus Routing Guidelines

Memory Interface Routing Guidelines

Hub Interface

82870P2 (P64H2)

I/O Controller Hub

Debug Port

EMI and Mechanical Design Considerations

Platform Power Delivery Guidelines

Schematic Checklist

Layout Checklist

Schematics

Intel Xeon Datasheet (96 pages)

Table of Contents

Introduction

Electrical Specifications

Mechanical Specifications

Signal Definitions

Pin List

Thermal Specifications

Features

Boxed Processor Specifications

Debug Tools Specifications

Intel Xeon Design Manual (44 pages)

Table of Contents

Intel Xeon User Manual (38 pages)

Table of Contents

1 Product Overview

2 Platform Management

3 Equipment Required for CRB Usage

4 Jumpers and Headers

5 System Overview

6 Debug Procedure

Intel Xeon Specification (56 pages)

Table of Contents

Intel Xeon Manuallines (11 pages)

Table of Contents

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