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This is always the case as the messages in the trace buffer vary in length. With two entries, the first
(oldest) entry that set a checkpoint in the trace buffer corresponds to CHKPT1, the second entry
that set a checkpoint corresponds to CHKPT0.
Although the checkpoint registers are provided for wrap-around mode, they are still valid in fill-
once mode.
10.11.1.2
Trace Buffer Register (TBREG)
The trace buffer is read through TBREG, using MRC and MCR. Software can only read the trace
buffer when it is disabled. Reading the trace buffer while it is enabled, will cause unpredictable
behavior of the trace buffer. Writes to the trace buffer have unpredictable results. Reading the trace
buffer returns the oldest byte in the trace buffer in the least significant byte of TBREG. The byte is
either a message byte or one byte of the 32 bit address associated with an indirect branch
message.Table 10-18 shows the format of the trace buffer register.
Table 10-18. TBREG Format
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
reset value: unpredictable
Bits
31:8
Read-as-Zero/Write-ignored
7:0
Read / Write-unpredictable
10.11.2
Trace Buffer Usage
The Intel® XScale™ core trace buffer is 256 bytes in length. The first byte read from the buffer
represents the oldest trace history information in the buffer. The last (256th) byte read represents
the most recent entry in the buffer. The last byte read from the buffer will always be a message
byte. This provides the debugger with a starting point for parsing the entries out of the buffer.
Because the debugger needs the last byte as a starting point when parsing the buffer, the entire trace
buffer must be read (256 bytes on the Intel® XScale™ core) before the buffer can be parsed.
Figure 10-6
Intel® XScale™ Microarchitecture User's Manual
Access
is a high level view of the trace buffer.
9
Description
Reserved
Message Byte or Address Byte
Software Debug
8
7
6
5
4
3
2
1
Data
10-25
0
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