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3.0
Routing Guidelines
The order in which signals are routed first and last varies from designer to designer. Some prefer to
route all clock signals first, while others prefer to route all high speed bus signals first. Either order
can be used, provided the guidelines listed here are followed.
Route the
This topology assumes that no stubs are used to connect any devices on the net.
two possible techniques to achieve a stubless trace. When it is not possible to apply one of these
two techniques due to congestion, a very short stub is allowed — preferably not to exceed
250 mils.
Figure 3-2.
Examples of Stubless and Short Stub Traces
3.1
Trace Length Limits
For add-in cards, trace lengths from the top of the card edge connector to the
are as follows:
•
The maximum trace length for all 32-bit interface signals should not exceed 1.5 inches for
32-bit and 64-bit cards. This includes all signals except those listed as 'Signal Pins', 'Interrupt
Pins', and 'JTAG Pins' as per PCI Local Bus Specification, Revision 2.1.
•
The trace length of the additional signals used in the 64-bit extension are limited to 2 inches on
all 64-bit cards.
•
The trace length for the PCI CLK signal is 2.5 inches ± 0.1 inch for 32-bit and 64-bit cards and
should be routed to only a single load.
Design Guide
RM/RN I/O processor
address/data and control signals using a "daisy chain" topology.
Stubless
Intel® i960® RM/RN I/O Processor
*
Routing Guidelines
Figure 3-2
shows
Short Stub
<250 mils
RM/RN I/O processor
11
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