Simple Terminations; Jtag Signal Layout Guidelines - Intel Pentium III Processor 512K Design Manual

® ®
LV Intel Pentium III Processor 512K Dual Processor Platform
Table 10. System Signal Layout Guidelines
POWERON
BCLK, BCLK#
DBRESET#, BSEN#,
DBINST#
Figure 6. Simple Terminations

JTAG Signal Layout Guidelines

Reflections on TCK that cause mid-threshold ringing will render the primary system debug tool
inoperative. Simulate the behavioral model, and verify signal integrity using your system bus
signal analysis tools. The following table provides the JTAG signal layout guidelines. It is highly
recommended that TCK be simulated to ensure proper signal quality is maintained.
Table 11. JTAG Signal Layout Guidelines
Signal
TCK
TMS, TDI,
TDO
TRST#
20
Signal
Route with normal trace 2 to 6 inches to the debug port
connector
Critical JTAG signal which requires timing and signal integrity
considerations; driver is 74VCX16245 with external edge rate control on
TCK
Critical JTAG signal which requires timing and signal integrity
considerations. ITP driver is 74VCX16245. TMS must be routed with TCK.
Pull-down resistors should be used to force TRST# assertion (low).
Routing Notes
Routing Notes
Sample Layout
Figure 6a
N/A
Figure 6a
Sample Layout
Figure 7
Figure 6a
Figure 6b
Design Guide