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•
If the AS configuration is failing due to a corrupt image inside the serial flash device and reprogramming does not resolve
the problem, you have two possible solutions depending on the components you are using for configuration:
— If you are using a third-party programmer to configure the flash directly from an AS or JTAG header as shown in
Figure 42
loading automatically at power-on. Then, update the image in quad serial flash through the AS or JTAG header.
— If you are programming the flash device using the JTAG header as shown in
nCONFIG
the image in quad serial flash through the JTAG header.
•
If you are using AS x4 flash memories with AS Fast mode, you must ramp up all power supplies to the recommended
operating condition within 10 ms. This ramp-up requirement ensures that the AS x4 device is within its operating voltage
range when the Intel Agilex device begins to access it.
•
Check endianness of the
the
as big endian.
.rpd
•
If you are using the
starts to load a bitstream from the Quad SPI device. The SDM starts configuration after the device exits the POR state if
nCONFIG is held high.
•
Try a lower AS clock frequency setting.
•
If you drive
•
If you pulse
follow the
nCONFIG
•
Ensure no external component drives the
3.3. JTAG Configuration
JTAG-chain device programming is ideal during development. JTAG-chain device configuration uses the JTAG pins to configure
the Intel Agilex FPGA directly with the
because it does not require you to program external flash memory. You can also use JTAG to reprogram if the image stored in
quad SPI memory. You can also use the JTAG configuration scheme to reprogram the quad SPI memory if the quad SPI
content is corrupted or invalid.
Intel
®
Agilex
™
Configuration User Guide
124
on page 111 change the
MSEL
signal to low. When
nCONFIG
if using a third-party programmer to program Quad SPI device. You should generate
.rpd
clock source for configuration, ensure
OSC_CLK_1
signal using the external host, ensure it remains high during the AS x4 configuration scheme.
nCONFIG
low for reconfiguration, ensure that the
nCONFIG
signal, the FPGA may not exit power on reset state. You may need to power cycle the PCB.
/
.sof
.rbf
setting to JTAG. Setting
MSEL
is low, the image cannot load from the quad SPI flash device. Then, update
OSC_CLK_1
nSTATUS
signal low during the power up.
nSTATUS
file. Configuration using the JTAG device chain allows faster development
3. Intel Agilex Configuration Schemes
to JTAG prevents the corrupt image from
Figure 43
on page 112, force the
is free running and stable before SDM
acknowledges
. If
nCONFIG
nSTATUS
683673 | 2021.10.29
does not
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