Test; Boundary-Scan Architecture And Overview - Intel PXA255 User Manual

Test

The application processor Test Access Port (TAP) conforms to the IEEE Std. 1149.1 – 1990, IEEE
Std. 1149.1a-1993, Standard Test Access Port and Boundary-Scan Architecture. Refer to this
standard for any explanations not covered in this section. This standard is more commonly referred
to as JTAG, an acronym for the Joint Test Action Group.
The JTAG interface on the application processor can be used as a hardware interface for software
debugging of PXA255 systems. This interface is described in
The JTAG hardware and test features of the application processor are discussed in the following
sections.
9.1

Boundary-Scan Architecture and Overview

The JTAG interface on the application processor provides a means of driving and sampling the
external pins of the device irrespective of the core state. This feature is known as boundary scan.
Boundary scan permits testing of both the device's electrical connections to the circuit board and
integrity of the circuit board connections between devices via linked JTAG interfaces. The
interface intercepts external connections within the device via a boundary-scan cell, and each such
"cell" is then connected together to form a serial shift register, called the boundary-scan register.
The boundary-scan test logic elements include the TAP pins, TAP Controller, instruction register,
and a set of test data registers including: boundary-scan register, bypass register, device
identification register, and data specific registers. This is shown in
Figure 9-1. Test Access Port (TAP) Block Diagram
TDI
TMS
TCK
nTRST
Intel® XScale™ Microarchitecture User's Manual
Instruction
Register/5
Boundary Scan Register
TAP
Controller
Control And Clock Signals
Chapter 10, "Software Debug."
Bypass Register/1
Device ID Register/32
Data Specific Register(s)
Figure 9-1.
9
TDO
9-1