Register 10: Tlb Lock Down; Register 13: Process Id - Intel PXA255 User Manual

Configuration
7.2.10

Register 10: TLB Lock Down

Register 10 is used for locking down entries into the instruction TLB, and data TLB. The protocol
for locking down entries can be found in
operations on a TLB when the MMU is disabled have an undefined effect.
This register is write-only. Reads from this register, as with an MRC, have an undefined effect.
Table 7-16
The entry to lock is specified by the virtual address in Rd.
Table 7-16. TLB Lockdown Functions
Translate and Lock I TLB entry
Translate and Lock D TLB entry
Unlock I TLB
Unlock D TLB
7.2.11

Register 13: Process ID

The Intel® XScale™ core supports the remapping of virtual addresses through a Process ID (PID)
register. This remapping occurs before the instruction cache, instruction TLB, data cache and data
TLB are accessed. The PID register controls when virtual addresses are remapped and to what
value.
The PID register is a 7-bit value that is ORed with bits 31:25 of the virtual address when they are
zero. This effectively remaps the address to one of 128 "slots" in the 4 Gbytes of address space. If
bits 31:25 are not zero, no remapping occurs. This feature is useful for operating system
management of processes that may map to the same virtual address space. In those cases, the
virtually mapped caches on the Intel® XScale™ core would not require invalidating on a process
switch.
Table 7-17. Accessing Process ID
Read Process ID Register
Write Process ID Register
7-12
shows the commands for locking down entries in the instruction TLB, and data TLB.
Function opcode_2
0b000
0b000
0b001
0b001
Function
Chapter 3, "Memory
CRm Data
0b0100 MVA
0b1000 MVA
0b0100 Ignored
0b1000 Ignored
opcode_2 CRm
0b000 0b0000
0b000 0b0000
Intel® XScale™ Microarchitecture User's Manual
Management". Lock/unlock
Instruction
MCR p15, 0, Rd, c10, c4, 0
MCR p15, 0, Rd, c10, c8, 0
MCR p15, 0, Rd, c10, c4, 1
MCR p15, 0, Rd, c10, c8, 1
Instruction
MRC p15, 0, Rd, c13, c0, 0
MCR p15, 0, Rd, c13, c0, 0