Common Memory Space Write Commands; Common Memory Space Read Commands; Attribute Memory Space Write Commands; Attribute Memory Space Read Commands - Intel PXA255 Developer's Manual

When writes goes to a card sockets and a byte has been masked via an internal byte enable, the
write does not occur on the external bus. For reads, one half-word is always read from the socket,
even if only 1 byte is requested. In some cases, based on internal address alignment, one word is
read, even if only 1 byte is requested.
All DMA modes are supported in the Card interface increment the address.
Table 6-31. Common Memory Space Write Commands
nPCE2 nPCE1 MA<0> nPOE
0
1
1
Table 6-32. Common Memory Space Read Commands
nPCE2 nPCE1 MA<0> nPOE
0
Table 6-33. Attribute Memory Space Write Commands
nPCE2 nPCE1 MA<0> nPOE
0
1
1
Table 6-34. Attribute Memory Space Read Commands
nPCE2 nPCE1 MA<0> nPOE
0
Table 6-35. 16-Bit I/O Space Write Commands (nIOIS16 = 0)
nPCE2 nPCE1 MA<0> nPIOR nPIOW
0
1
1
Table 6-36. 16-Bit I/O Space Read Commands (nIOIS16 = 0)
nPCE2 nPCE1 MA<0> nPIOR nPIOW
0
Intel® PXA255 Processor Developer's Manual
nPWE
0 0 1 0
0 0 1 0
0 1 1 0
nPWE
0 0 0 1
nPWE
0 0 1 0
0 0 1 0
0 1 1 0
nPWE
0 0 0 1
0 0 1 0
0 0 1 0
0 1 1 0
0 0 0 1
MD[15:8] MD[7:0]
Odd Byte Even Byte
Unimportant Even Byte
Unimportant Odd Byte
MD[15:8] MD[7:0]
Odd Byte Even Byte
MD[15:8] MD[7:0]
Unimportant Even Byte
Unimportant Even Byte
Unimportant Unimportant
MD[15:8] MD[7:0]
Unimportant Even Byte
MD[15:8] MD[7:0]
Odd Byte Even Byte
Unimportant Even Byte
Unimportant Odd Byte
MD[15:8] MD[7:0]
Odd Byte Even Byte
Memory Controller
6-65