Platform Interrupt Mask/Enable Register (Intmskena); Intmsken Bit Definitions High Bits; Intmsken Bit Definitions Low Bits - Intel PXA27x User Manual

3.2.2.9

Platform Interrupt Mask/Enable Register (INTMSKENA)

INTMSKENA, defined in
table. To enable an interrupt, set its corresponding bit. To mask it, clear its bit.
For details of the kit interrupt controller, see
Table 26
Table 27
Note: Ignore reads from reserved bits. Write 0b0 to reserved bits.
Table 26. INTMSKEN Bit Definitions High Bits
Physical Address: 0x0800_00C0
Bit 31 30 29
Name
Reset ? ? ?
Bits Name
31-20 reserved
19 INT_Mx
18 BT_RI_INT
17 BT_DTR_INT
16 PMC_IRQ
Table 27. INTMSKEN Bit Definitions Low Bits (Sheet 1 of 2)
Physical Address: 0x0800_00C0
Bit 15 14 13
Name
Reset 0 0 0
Bits Name
15 S1_IRQ
14 S1_STSCHG
13 S1_CD
12 —
11 S0_IRQ
10 S0_STSCHG
®
Intel PXA27x Processor Developer's Kit - User's Guide
Table 27, provides for masking and enabling the interrupts listed in the
defines the high bit definitions. (31-16).
defines the low bit definitions.(15-0).
28 27 26 25
Reserved
? ? ? ?
Access Description
R/W reserved
R/W Graphics Accelerator Interrupt Request
R/W Bluetooth Ring Indicator Interrupt Request
R/W Bluetooth UART Data Terminal Ready Interrupt Request
R/W Power Management IC Interrupt Request
12 11 10 9
? 0 0 0
Access Description
R/W PCMCIA socket 1 interrupt request (IRQ)
R/W PCMCIA socket 1 status changed
R/W PCMCIA socket 1 card detection
— reserved
R/W PCMCIA socket 0 IRQ
R/W PCMCIA socket 0 status changed
Section 3.4.
INTMSKEN Intel
24 23 22 21
? ? ? ?
INTMSKEN Intel
8 7 6 5
? 0 0 0
®
PXA27x Processor Developer's Kit
20 19 18 17
? 0 0 0
®
PXA27x Processor Developer's Kit
4 3 2 1
0 0 0 0
16
0
0
0
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