4.3.10 Interrupt Acknowledge - Intel Embedded Intel486 Hardware Reference Manual

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL

4.3.10 Interrupt Acknowledge

The Intel486 processor generates interrupt acknowledge cycles in response to maskable interrupt
requests that are generated on the interrupt request input (INTR) pin. Interrupt acknowledge cy-
cles have a unique cycle type generated on the cycle type pins.
An example of an interrupt acknowledge transaction is shown in
edge cycles are generated in locked pairs. Data returned during the first cycle is ignored. The in-
terrupt vector is returned during the second cycle on the lower 8 bits of the data bus. The Intel486
processor has 256 possible interrupt vectors.
The state of A2 distinguishes the first and second interrupt acknowledge cycles. The byte address
driven during the first interrupt acknowledge cycle is 4 (A31–A3 low, A2 high, BE3#–BE1#
high, and BE0# low). The address driven during the second interrupt acknowledge cycle is 0
(A31–A2 low, BE3#–BE1# high, BE0# low).
Each of the interrupt acknowledge cycles is terminated when the external system asserts RDY#
or BRDY#. Wait states can be added by holding RDY# or BRDY# deasserted. The Intel486 pro-
cessor automatically generates four idle clocks between the first and second cycles to allow for
8259A recovery time.
Ti
CLK
ADS#
ADDR
RDY#
DATA
LOCK#
†
To Processor
4-40
T1 T2 Ti
4 Clocks
04
Figure 4-31. Interrupt Acknowledge Cycles
Figure 4-31. Interrupt acknowl-
Ti T1 T2
00
†
Ti
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