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INTERRUPT CONTROL UNIT
8.4.2
Interrupt Request Register
The Interrupt Request register (Figure 8-7) has one bit for each interrupt source. When a source
requests an interrupt, its Interrupt Request bit is set (without regard to whether the interrupt is
masked). The Interrupt Request bit is cleared when the interrupt is acknowledged. An external
interrupt pin must remain asserted until its interrupt is acknowledged. Otherwise, the Interrupt
Request bit will be cleared, but the interrupt will not be serviced.
Register Name:
Register Mnemonic:
Register Function:
15
Bit
Mnemonic
INT3:0
External
Interrupts
DMA1:0
DMA
Interrupt
TMR
Timer
Interrupt
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.
8.4.3
Interrupt Mask Register
The Interrupt Mask register (Figure 8-8) contains a mask bit for each interrupt source. This reg-
ister allows you to mask (disable) individual interrupts. Set a mask bit to disable interrupts from
the corresponding source. The mask bit is the same as the one in the Interrupt Control register.
Modifying a bit in either register also modifies that same bit in the other register.
8-16
Interrupt Request Register
REQST
Stores pending interrupt requests
Reset
Bit Name
State
0000 0
0
0
Figure 8-7. Interrupt Request Register
I
I
I
I
N
N
N
N
T
T
T
T
3
2
1
0
Function
A bit is set to indicate a pending interrupt from
the corresponding external interrupt pin.
A bit is set to indicate a pending interrupt from
the corresponding DMA channel.
This bit is set to indicate a pending interrupt
from one of the timers.
0
D
D
T
M
M
M
A
A
R
1
0
A1201-A0
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