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Intel XScale® Microarchitecture & Intel® Wireless MMX™ Technology Optimization
4.10
Performance Hazards
The basic performance of the system can be effected by stalls caused by data or resource hazards.
This section describes the factors effecting each type of hazard and the implications for
performance.
4.10.1
Data Hazards
A data hazard occurs when an instruction requires data that cannot be provided by the register file
or the data-forwarding mechanism or if two instructions update the same destination register in an
out of order fashion. The first hazard is termed as Read-After-Write (RAW) and the second hazard is
termed as Write-After-Write (WAW). The processing of the new instruction is stalled until the data
becomes available for RAW hazards, and until it can be guaranteed that the new instruction will
update the register file after previous instruction has updated the same destination register, for
WAW hazards. The PXA27x processor device contains a bypassing mechanism for ensuring that
data and different stages of the pipeline can forwarded to the correct instructions. There are,
however, certain combinations of instructions where it is not possible to forward directly between
instructions in the PXA27x processor 1.0 implementation.
The result latency shown in
However there are certain instruction combinations where these result latencies do not hold
because not all combinations of bypassing logic exist in the hardware, and some instructions
require more time to calculate the result when certain qualifiers are specified. This list describes the
data hazards for the PXA27x processor 1.0 implementation:
•
When saturation is specified for WADD or WSUB, the result latency is increased to two cycles
•
The destination register (accumulator) for certain multiplier instructions (WMAC, WSAD,
TMIA, TMIAph, TMIAxy) can be forwarded for accumulation to the same destination register
only. If the destination register results are needed by another instruction as source operands,
there is an additional result latency as the result is available from the regular forwarding paths,
external to the multiplier. The exact number of extra cycles depends upon the multiplier
instruction that is delivering results to source operands of other instructions.
•
If an instruction is updating a destination register from the multiply pipeline, a following
instruction in the execute, memory or core interface pipelines updating the same destination
register is stalled till it can be guaranteed that the following instruction will update the register
file after the previous instruction in the multiply pipe, has updated the register file
•
If an instruction is updating a destination register from the memory pipeline, a following
instruction updating the same destination register is stalled till it can be guaranteed that the
following instruction will update the register file after the previous instruction in the memory
pipe, has updated the register file.
•
If the Intel XScale® Microarchitecture MAC unit is in use, the resulting latency of a TMRC,
TMRRC, and TEXRM increases accordingly.
4.10.2
Resource Hazard
A resource hazard is caused when an instruction requires a resource that is already in use. When
this condition is detected, the processing of the new instruction is stalled at the register file stage.
Intel® PXA27x Processor Family Optimization Guide
Table 4-18
and best-case result latency are generally achievable.
4-45
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