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Table 7-18. Process ID Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Process ID
reset value: 0x0000_0000
Bits
31:25
24:0
7.2.11.1
The PID Register Affect On Addresses
All addresses generated and used by User Mode code are eligible for being translated using the PID
register. Privileged code however, must be aware of certain special cases in which address
generation does not follow the usual flow.
•
The PID register is not used to remap the virtual address when accessing the Branch Target
Buffer (BTB). Debug software reading the BTB needs to recognize addresses as MVAs. Any
write to the PID register invalidates the BTB. This prevents any virtual addresses after the PID
has changed from matching the incorrect Branch Target of any previously running process.
•
A breakpoint address (see
must be expressed as an MVA when written to the breakpoint register. This means the value of the
PID must be combined appropriately with the address before it is written to the breakpoint
register. All virtual addresses in translation descriptors (see
are MVAs.
7.2.12
Register 14: Breakpoint Registers
The Intel® XScale™ core contains two instruction breakpoint address registers (IBCR0 and
IBCR1), one data breakpoint address register (DBR0), one configurable data mask/address register
(DBR1), and one data breakpoint control register (DBCON). The Intel® XScale™ core also
supports a 2K byte mini instruction cache for debugging and a 256 entry trace buffer that records
program execution information. The registers to control the trace buffer are located in CP14.
Refer to
Chapter 10, "Software Debug"
XScale™ core.
Table 7-19. Accessing the Debug Registers (Sheet 1 of 2)
Read Instruction Breakpoint
Register 0 (IBCR0)
Write IBCR0
Read Instruction Breakpoint
Register 1 (IBCR1)
Write IBCR1
Read Data Breakpoint 0 (DBR0)
Intel® XScale™ Microarchitecture User's Manual
Access
Read / Write
Read-as-Zero / Write-as-Zero
Section 7.2.12, "Register 14: Breakpoint Registers" on page
Function
opcode_2
Process ID - This field is used for remapping the virtual
address when bits 31-25 of the virtual address are zero.
Reserved - Must be programmed to zero for future
compatibility
Chapter 3, "Memory
for more information on these features of the Intel®
CRm
0b000
0b1000
0b000
0b1000
0b000
0b1001
0b000
0b1001
0b000
0b0000
Configuration
8
7
6
5
4
3
2
Description
7-13)
Management")
Instruction
MRC p15, 0, Rd, c14, c8, 0
MCR p15, 0, Rd, c14, c8, 0
MRC p15, 0, Rd, c14, c9, 0
MCR p15, 0, Rd, c14, c9, 0
MRC p15, 0, Rd, c14, c0, 0
1
0
7-13
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