Using The Interrupt Request Latch Registers - Intel 80C188EC User Manual

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Using the Interrupt Request Latch Registers

An interrupt handler for an on-board peripheral must clear that peripheral's Interrupt Request

Latch bit before issuing an EOI to the slave 8259A. Otherwise, the IR line to the slave 8259A

module remains high, requesting another interrupt. The three Interrupt Request Registers

(DMAIRL, SCUIRL and TIMIRL) are shown in Figures 8-24, 8-25 and 8-26. All three registers

function identically.

The state of the IR (interrupt request latch) bits can be changed only when the corresponding

mask bit is set. For example, to clear an interrupt request from Timer 0, you must write a word to

the TIMRL register with the T0IR bit cleared and the MSK0 bit set. The IRL bits can be read as

well as written; the MSK bits always read back as zero.

To Slave 8259A Module

Internal Data Bus

Figure 8-23. Multiplexed Interrupt Requests

INTERRUPT CONTROL UNIT