Test Load Vs. Actual System Load - Intel 810A3 Design Manual

Figure 5-2. Test Load vs. Actual System Load
Figure 5-2
flip-flop represents the logic input and driver stage of a typical AGTL+ I/O buffer. T
specified at the driver pin output. T
time from the driver pad starting its transition to the time when the receiver's input pin sees a valid
data input. Since both timing numbers (T
the pad to the pin, it is necessary to subtract this time (T
double counting. T
measurement voltage, V
must be generated using the same test load for T
I/O buffer models.
In this manner, the following valid delay equation is satisfied:
Equation 5-5. Valid Delay Equation
This valid delay equation is the total time from when the driver sees a valid clock pulse to the time
when the receiver sees a valid data input.
5.1.6.3 Flight Time Hardware Validation
When a measurement is made on the actual system, T
correction since these are the actual numbers. These measurements include all of the effects
pertaining to the driver-system interface and the same is true for the T
the measured T
®
Intel 810A3 Chipset Design Guide
I/O Buffer
Vcc
SET
D
CLK
CLR
I/O Buffer
Vcc
SET
D
CLK
CLR
above shows the different configurations for T
FLIGHT-SYSTEM
is defined as the time that it takes for the driver output pin to reach the
REF
, starting from the beginning of the driver transition at the pad. T
REF
Valid Delay = T
CO
and the measured flight time must be equal to the valid delay calculated above.
CO
V
TT
Driver
R Test Load
TEST
Pad
Driver
Q
Pin
Q
T
R E F
T
C O
Actual
System
Load
Driver
Pad
Q
Q
T
F L I G H T S Y S T E M
testing and flight time simulation. The
CO
is usually reported by a simulation tool as the
and T
CO FLIGHT-SYSTEM
) from the reported flight time to avoid
REF
. Intel provides this timing value in the AGTL+
CO
+ T - T = T
FLIGHT-SYS REF
and flight time do not need T
CO
Advanced System Bus Design
V
TT
R
TT
Receiver
Pin
timings are
CO
) include propagation time from
+ T
CO-MEASURED FLIGHT-MEASURED
REF
. Therefore the addition of
CO
REF
5-9