Table 3-12 Ipcmmisx Register Bit Assignments; Table 3-13 Ipcmrisx Register Bit Assignments; Figure 3-6 Mailbox Status - ARM PrimeCelL PL320 Technical Reference Manual

Programmer's Model
3.3.12 Raw Interrupt Status Registers
3.3.13 Configuration Status Register
3-18
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IPCM0MASK[0]
IPCM0SEND[0]
IPCM0DEST[0]
IPCM0SEND[1]
IPCM0SOURCE[0]
The Masked Interrupt Status Registers identify which mailbox triggered the interrupt.
This value is the logical AND of the raw interrupt status with the Mailbox Mask Status
Registers. All Masked Interrupt Status Register outputs are ORed together to form the
IPCMINT[31:0] interrupt output bus.
Table 3-12 lists the register bit assignments.
The read-only IPCMRISx Registers indicate the unmasked interrupt status of each
mailbox for each core.
Table 3-13 lists the register bit assignments.
The read-only IPCMCFGSTAT Register indicates the hardware configuration options
chosen for implementation of the IPCM.
Figure 3-7 on page 3-19 shows the register bit assignments.
Copyright © 2003, 2004. ARM Limited. All rights reserved.

Figure 3-6 Mailbox status

Table 3-12 IPCMMISx Register bit assignments

Bit Name
[31:0] MaskIntStat

Table 3-13 IPCMRISx Register bit assignments

Bit Name
[31:0] RawIntStat
IPCMMIS0[0]
IPCMRIS0[0]
Function
Masked interrupt status
Function
Raw interrupt status
ARM DDI 0306B