About This Book - ARM Cortex-A76 Core Technical Reference Manual

About this book

This Technical Reference Manual is for the Cortex
contains programming details for registers. It also describes the memory system, the caches, the
interrupts, and the debug features.
Product revision status
The r p
m n
where:
r Identifies the major revision of the product, for example, r1.
m
p Identifies the minor revision or modification status of the product, for example, p2.
n
Intended audience
This manual is for system designers, system integrators, and programmers who are designing or
programming a System-on-Chip (SoC) that uses an Arm core.
Using this book
This book is organized into the following chapters:
Part A Functional description
This part describes the main functionality of the Cortex-A76 core.
Chapter A1 Introduction
This chapter provides an overview of the Cortex-A76 core and its features.
Chapter A2 Technical overview
This chapter describes the structure of the Cortex-A76 core.
Chapter A3 Clocks, resets, and input synchronization
This chapter describes the clocks, resets, and input synchronization of the Cortex-A76 core.
Chapter A4 Power management
This chapter describes the power domains and the power modes in the Cortex-A76 core.
Chapter A5 Memory Management Unit
This chapter describes the Memory Management Unit (MMU) of the Cortex-A76 core.
Chapter A6 Level 1 memory system
This chapter describes the L1 instruction cache and data cache that make up the L1 memory
system.
Chapter A7 Level 2 memory system
This chapter describes the L2 memory system.
Chapter A8 Reliability, Availability, and Serviceability (RAS)
This chapter describes the RAS features implemented in the Cortex-A76 core.
Chapter A9 Generic Interrupt Controller CPU interface
This chapter describes the Cortex-A76 core implementation of the Arm Generic Interrupt
Controller (GIC) CPU interface.
Chapter A10 Advanced SIMD and floating-point support
This chapter describes the Advanced SIMD and floating-point features and registers in the
Cortex-A76 core. The unit in charge of handling the Advanced SIMD and floating-point features
is also referred to as data engine in this manual.
Part B Register descriptions
This part describes the non-debug registers of the Cortex-A76 core.
100798_0300_00_en
identifier indicates the revision status of the product described in this book, for example, r
Copyright © 2016–2018 Arm Limited or its affiliates. All rights
-A76 core. It provides reference documentation and
®
reserved.
Non-Confidential
Preface
Product revision status
p ,
1 2
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