Gpio Port Configuration Lock Register (Gpiox_Lckr); (X = A - ST STM32F205 series Reference Manual

General-purpose I/Os (GPIO)
Bits 31:16 BRy: Port x reset bit y (y = 0..15)
Note: If both BSx and BRx are set, BSx has priority.
Bits 15:0 BSy: Port x set bit y (y= 0..15)
6.4.8

GPIO port configuration lock register (GPIOx_LCKR)

(x = A..I)
This register is used to lock the configuration of the port bits when a correct write sequence
is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the
GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the
LOCK sequence has been applied on a port bit, the value of this port bit can no longer be
modified until the next MCU or peripheral reset.
Note: A specific write sequence is used to write to the GPIOx_LCKR register. Only word access
(32-bit long) is allowed during this write sequence.
Each lock bit freezes a specific configuration register (control and alternate function
registers).
Address offset: 0x1C
Reset value: 0x0000 0000
Access: 32-bit word only, read/write register
31 30 29
15 14 13
LCK15 LCK14 LCK13 LCK12
rw rw rw
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These bits are write-only and can be accessed in word, half-word or byte mode. A read to
these bits returns the value 0x0000.
0: No action on the corresponding ODRx bit
1: Resets the corresponding ODRx bit
These bits are write-only and can be accessed in word, half-word or byte mode. A read to
these bits returns the value 0x0000.
0: No action on the corresponding ODRx bit
1: Sets the corresponding ODRx bit
28 27 26 25
12 11 10 9
LCK11 LCK10 LCK9
rw rw rw rw
24 23 22
Reserved
8 7 6
LCK8 LCK7 LCK6
rw rw rw
RM0033 Rev 8
21 20 19 18
5 4 3 2
LCK5 LCK4 LCK3 LCK2
rw rw rw rw
RM0033
17 16
LCKK
rw
1 0
LCK1 LCK0
rw rw