Rcc Ahb3 Peripheral Clock Enable In Sleep And Stop Mode Register (Rcc_Ahb3Smenr) - ST STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution

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RCC AHB3 peripheral clock enable in Sleep and Stop mode register

(RCC_AHB3SMENR)

Address offset: 0x070

Reset value: 0x0387 0000

Access: no wait state, word, half-word and byte access

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 FLASHSMEN: Flash memory interface clock enable during CPU1 CSleep mode.

Bit 24 SRAM2SMEN: SRAM2 memory interface clock enable during CPU1 CSleep mode

Bit 23 SRAM1SMEN: SRAM1 interface clock enable during CPU1 CSleep mode.

Bits 22:19 Reserved, must be kept at reset value.

Bit 18 RNGSMEN: True RNG clocks enable during CPU1 CSleep and CStop modes

This bit is set and cleared by software.

0: Flash memory interface clock disabled by the clock gating during CPU1 CSleep and

1: Flash memory interface clock enabled by the clock gating during CPU1 CSleep mode,

disabled during CPU1 CStop mode.

This bit is set and cleared by software.

0: SRAM2 clock disabled by the clock gating during CPU1 CSleep and CStop modes

1: SRAM2 clock enabled by the clock gating during CPU1 CSleep mode, disabled during

CPU1 CStop mode.

This bit is set and cleared by software.

0: SRAM1 interface clock disabled by the clock gating during CPU1 CSleep and CStop

1: SRAM1 interface clock enabled by the clock gating during CPU1 CSleep mode, disabled

during CPU1 CStop mode

This bit is set and cleared by software.

0: True RNG bus clock disabled by the clock gating during CPU1 CSleep and CStop modes

1: True RNG bus clock enabled by the clock gating during CPU1 CSleep mode, disabled

during CPU1 CStop mode.

RM0453 Rev 1

Reset and clock control (RCC)

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