Dac Register Map; Table 52. Dac Register Map - ST STM32F102 Series Reference Manual

RM0008
11.5.14

DAC register map

The following table summarizes the DAC registers.
Table 52. DAC Register map
Ad-
dress Name
offset
0x00 DAC_CR
Reserved
DAC_SWTRI
0x04
GR
DAC_DHR12
0x08
R1
DAC_DHR12
0x0C
L1
DAC_DHR8R
0x10
1
DAC_DHR12
0x14
R2
DAC_DHR12
0x18
L2
DAC_DHR8R
0x1C
2
DAC_DHR12
0x20 Reserved
RD
DAC_DHR12
0x24
LD
DAC_DHR8R
0x28
D
0x2C DAC_DOR1
0x30 DAC_DOR2
Note: Refer to
WAV
MAMP2[3:0] E2[2:
0]
Reserved
Reserved
Reserved
Reserved
DACC2DHR[11:0]
DACC2DHR[11:0]
Reserved
Reserved
Reserved
Table 1 on page 36 for the register boundary addresses.
TSEL2[2:
Reserved
0]
Reserved
Reserved
Reserved
Reserved
Reserved
DACC2DHR[7:0]
Digital-to-analog converter (DAC)
WAV
TSEL1[2:
MAMP1[3:0] E1[2:
0]
DACC1DHR[11:0]
DACC1DHR[11:0]
DACC1DHR[7:0]
DACC2DHR[11:0]
DACC2DHR[11:0]
DACC2DHR[7:0]
DACC1DHR[11:0]
DACC1DHR[11:0]
DACC1DHR[7:0]
DACC1DOR[11:0]
DACC2DOR[11:0]
0
0]
Reserved
Reserved
Reserved
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