Dac Status Register (Dac_Sr); Dac Register Map; Table 43. Dac Register Map - ST STM32F205 series Reference Manual

Advanced arm-based 32-bit mcus

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Digital-to-analog converter (DAC)

DAC status register (DAC_SR)

Address offset: 0x34

Reset value: 0x0000 0000

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 DMAUDR2: DAC channel2 DMA underrun flag

Bits 28:14 Reserved, must be kept at reset value.

Bit 13 DMAUDR1: DAC channel1 DMA underrun flag

Bits 12:0 Reserved, must be kept at reset value.

Offset Register

This bit is set by hardware and cleared by software (by writing it to 1).

0: No DMA underrun error condition occurred for DAC channel2

1: DMA underrun error condition occurred for DAC channel2 (the currently selected trigger is

driving DAC channel2 conversion at a frequency higher than the DMA service capability rate)

This bit is set by hardware and cleared by software (by writing it to 1).

0: No DMA underrun error condition occurred for DAC channel1

1: DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is

driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)

summarizes the DAC registers.

RM0033 Rev 8

DACC1DHR[11:0]

DACC1DHR[7:0]

DACC2DHR[11:0]

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