Debug support (DBG)
46.17.7
Asynchronous mode
This is a low cost alternative to output the trace using only 1 pin: this is the asynchronous
output pin TRACESWO. Obviously there is a limited bandwidth.
TRACESWO is multiplexed with JTDO when using the SW-DP pin. This way, this
functionality is available in all STM32G4 Series packages.
This asynchronous mode requires a constant frequency for TRACECLKIN. For the standard
UART (NRZ) capture mechanism, 5% accuracy is needed. The Manchester encoded
version is tolerant up to 10%.
46.17.8
TRACECLKIN connection inside the
STM32G4 Series
In the STM32G4 Series, this TRACECLKIN input is internally connected to HCLK. This
means that when in asynchronous trace mode, the application is restricted to use time
frames where the CPU frequency is stable.
Note:
Important: when using asynchronous trace: it is important to be aware that:
The default clock of the STM32G4 Series MCUs is the internal RC oscillator. Its frequency
under reset is different from the one after reset release. This is because the RC calibration
is the default one under system reset and is updated at each system reset release.
Consequently, the trace port analyzer (TPA) should not enable the trace (with the
TRACE_IOEN bit) under system reset, because a Synchronization Frame Packet will be
issued with a different bit time than trace packets which will be transmitted after reset
release.
2070/2083
RM0440 Rev 1
RM0440
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