ST STM32G4 Series Reference Manual page 2029

RM0440
Bit 6 TXUNDIE: Enable TXUND interrupt
This register can only be updated when UCPDEN=1.
0: Disabled
1: Enabled
Bit 5 HRSTSENTIE: Enable HRSTSENT interrupt
This register can only be updated when UCPDEN=1.
0: Disabled
1: Enabled
Bit 4 HRSTDISCIE: Enable HRSTDISC interrupt
This register can only be updated when UCPDEN=1.
0: Disabled
1: Enabled
Bit 3 TXMSGABTIE: Enable TXMSGABT interrupt
This register can only be updated when UCPDEN=1.
0: Disabled
1: Enabled
Bit 2 TXMSGSENTIE: Enable TXMSGSENT interrupt
This register can only be updated when UCPDEN=1.
0: Disabled
1: Enabled
Bit 1 TXMSGDISCIE: Enable TXMSGDISC interrupt
This register can only be updated when UCPDEN=1.
0: Disabled
1: Enabled
Bit 0 TXISIE: Enable TXIS interrupt
This register can only be updated when UCPDEN=1.
0: Disabled
1: Enabled
45.7.5 UCPD Status Register (UCPD_SR)
Address offset: 0x014
Reset value: 0x0000 0000
This register is used for status.
31 30 29
Res. Res. Res. Res.
28 27 26 25
Res. Res. Res.
USB Type-C™ / USB Power Delivery interface (UCPD)
24 23 22
Res. Res. Res.
RM0440 Rev 1
21 20 19 18
Res.
r r
17 16
r
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