ST STM32G4 Series Reference Manual page 2061

RM0440
46.16.2 Debug support for timers, RTC, watchdog and I
During a breakpoint, it is necessary to choose how the counter of timers,RTC and watchdog
should behave:
•
They can continue to count inside a breakpoint. This is usually required when a PWM is
controlling a motor, for example.
• They can stop to count inside a breakpoint. This is required for watchdog purposes.
2
For the I
The DBGMCU freeze registers can be written by the debugger under system reset. If the
debugger host does not support these features, it is still possible to write these registers by
software.
46.16.3 Debug MCU configuration register (DBGMCU_CR)
Address: 0xE004 2004
Power-on reset: 0x0000 0000
System reset: not affected
Access: Only 32-bit access supported
31 30 29
Res. Res. Res.
15 14 13
Res. Res. Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:5 TRACE_MODE[1:0] and TRACE_IOEN: Trace pin assignment control
– With TRACE_IOEN=0:
– With TRACE_IOEN=1:
Bits 4:3 Reserved, must be kept at reset value.
C, the user can choose to block the SMBUS timeout during a breakpoint.
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
Res. Res. Res. Res.
TRACE_MODE=xx: TRACE pins not assigned (default state)
– TRACE_MODE=00: TRACE pin assignment for Asynchronous Mode
– TRACE_MODE=01: TRACE pin assignment for Synchronous Mode with a
TRACEDATA size of 1
– TRACE_MODE=10: TRACE pin assignment for Synchronous Mode with a
TRACEDATA size of 2
– TRACE_MODE=11: TRACE pin assignment for Synchronous Mode with a
TRACEDATA size of 4
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
TRACE_ TRACE
Res. MODE _
[1:0] IOEN
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RM0440 Rev 1
Debug support (DBG)
2
C
20 19 18 17
Res. Res. Res. Res.
4 3 2 1
DBG_
DBG_
Res. Res. STAND
STOP
BY
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16
Res.
0
DBG_
SLEEP
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