ST STM32G4 Series Reference Manual page 2031

RM0440
Bit 11 RXOVR: Rx data overflow interrupt
This bit detects an error condition whereby the buffer of Rx bytes has overrun (not read in time
to free space for the incoming byte). It is cleared by writing 1 to RXOVRCF.
0: No Rx data overrun has occurred
1: An Rx data overrun has occurred
Bit 10 RXHRSTDET: Rx Hard Reset detect interrupt
This bit signals the reception of a Hard Reset message. It is cleared by writing 1 to
RXHRSTDETCF.
0: No Rx "Hard Reset" message has been correctly received
1: An Rx "Hard Reset" message has been correctly received
Bit 9 RXORDDET: Rx ordered set (4 K-codes) detected interrupt
This bit signals that an ordered set has been detected. The relevant information is stored in
field RXORDSET of register UCPD_RX_ORDSET. It is cleared by writing 1 to RXORDDETCF.
0: No ordered set has been detected (since last clear)
1: A new ordered set has been detected (since last clear)
Bit 8 RXNE: Receive data register not empty interrupt
This bit is set by hardware when the UCPD_RXDR register is not empty. It is cleared when
UCPD_RXDR is read.
0: Rx data register empty
1: Rx data register not empty
Bit 7 Reserved
Bit 6 TXUND: Tx data underrun condition interrupt
This bit detects an error condition whereby the Tx data register (TXDR) has under-run (i.e. data
was not written in time for use in Transmit message). It is cleared by writing 1 to TXUNDCF.
0: No Tx data underrun has occurred (since last clear via TXUNDCF)
1: A Tx data underrun has occurred (since last clear via TXUNDCF)
Bit 5 HRSTSENT: HRST sent interrupt
This bit signals that the HRST message has been sent (as TXMSGSENT but for Hard Reset). It
is cleared by writing 1 to HRSTSENTCF.
0: No HRST message sent interrupt
1: HRST message sent interrupt
Bit 4 HRSTDISC: HRST discarded interrupt
This bit signals that the HRST message has been discarded (as TXMSGDISC but for Hard
Reset). It is cleared by writing 1 to HRSTDISCCF.
0: No HRST discarded interrupt
1: HRST discarded interrupt
Bit 3 TXMSGABT: Transmit message abort interrupt
This bit will be set when a Tx message has been aborted due to a subsequent HRST send
request taking priority during transmit. It is cleared by writing 1 to TXMSGABTCF.
0: No transmit message abort interrupt
1: Transmit message abort interrupt
USB Type-C™ / USB Power Delivery interface (UCPD)
RM0440 Rev 1 2031/2083
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