ST STM32G4 Series Reference Manual page 2048

Debug support (DBG)
46.6.1 MCU device ID code
The STM32G4 Series MCUs integrate an MCU ID code. This ID identifies the ST MCU part-
number and the die revision. It is part of the DBG_MCU component and is mapped on the
external PPB bus (see
JTAG debug port (4 to 5 pins) or the SW debug port (two pins) or by the user software. It is
even accessible while the MCU is under system reset.
Only the DEV_ID(11:0) should be used for identification by the debugger/programmer tools.
DBGMCU_IDCODE
Address: 0xE004 2000
Only 32-bits access supported. Read-only
31 30 29 28
r r r
15 14 13 12
Res. Res. Res. Res.
Bits 31:16 REV_ID[15:0] Revision identifier
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 DEV_ID[11:0]: Device identifier
– 0x468: Category 2 devices (See
– 0x469: Category 3 devices (See
46.6.2 Boundary scan TAP
JTAG ID code
The TAP of the STM32G4 Series BSC (boundary scan) integrates a JTAG ID code equal to
16469041 (category 3 devices), 16468041 (category 2 devices).
46.6.3 Cortex
The TAP of the Arm
®
Arm default one and has not been modified. This code is only accessible by the JTAG
Debug Port.
This code is 0x4BA00477 (corresponds to Cortex
Reference Arm®
2048/2083
Section 46.16 on page
27 26 25
r r r r
11 10 9
r r r
This field indicates the revision of the device.
0x1000: Revision A
0x2000: Revision B
0x2001: Revision Z
The device ID is:
®
-M4 with FPU TAP
® ®
Cortex -M4 with FPU integrates a JTAG ID code. This ID code is the
documentation).
2060). This code is accessible using the
24 23 22
REV_ID[15:0]
r r r
8 7 6
DEV_ID[11:0]
r r r
Table 1: STM32G4 Series memory
Table 1: STM32G4 Series memory
®
-M4 with FPU r0p1, see
RM0440 Rev 1
21 20 19 18
r r r r
5 4 3 2
r r r r
density)
density)
Section 46.2:
RM0440
17 16
r r
1 0
r r