ST STM32G4 Series Reference Manual page 2032

USB Type-C™ / USB Power Delivery interface (UCPD)
Bit 2 TXMSGSENT: Transmit message sent interrupt. This is the confirmation at the end of every
transmit packet that the packet has been completely sent. In one specific case (subsequent
interruption by a Hard Reset which truncates the current message), the bit will not be raised. It
is cleared by writing 1 to TXMSGSENTCF.
0: Tx message has not (yet) been correctly sent
1: Tx message has been correctly sent
Bit 1 TXMSGDISC: Transmit message discarded interrupt
Transmit of message was not possible due to receive in progress (or noise on the line).
Although the Tx message will not be transmitted if non-IDLE state is true, this bit becomes true
only when CC becomes IDLE. This applies to all types of Tx messages, including Hard Reset
and BIST cases. It is cleared by writing 1 to TXMSGDISCCF.
0: No Tx message has been discarded
1: A Tx message has been discarded
Bit 0 TXIS: Transmit interrupt status
This bit is set by hardware when the UCPD_TXDR register is empty and it needs to be written
(i.e. until the last byte of the payload defined by TXPAYSZ). It is cleared when the next data to
be sent is written to the UCPD_TXDR register.
0: Tx data register not empty (or empty, but not awaiting data)
1: Tx data register empty and needs to be written
45.7.6 UCPD Interrupt Clear Register (UCPD_ICR)
Address offset: 0x018
Reset value: 0x0000 0000
This register is used for interrupt flag clearing.
31 30 29
Res. Res. Res. Res.
15 14 13
Res.
w w
Bits 31:21 Reserved
Bit 20 FRSEVTCF: FRS event flag (FRSEVT) clear
This register can only be updated when UCPDEN=1.
Writing 1 to this bit clears the FRSEVT flag in the UCPD_SR register
Bits 19:16 Reserved
Bit 15 TYPECEVT2CF: TypeC event (CC2) flag (TYPECEVT2) clear
This register can only be updated when UCPDEN=1.
Writing 1 to this bit clears the TYPECEVT2 flag in the UCPD_SR register
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28 27 26 25
Res. Res. Res.
12 11 10 9
w w w w
24 23 22
Res. Res. Res.
8 7 6
Res. Res.
w
RM0440 Rev 1
21 20 19 18
Res. Res. Res.
w
5 4 3 2
w w w w
RM0440
17 16
Res. Res.
1 0
Res.
w