ST STM32G4 Series Reference Manual page 2062

Debug support (DBG)
Bit 2 DBG_STANDBY: Debug Standby mode
Bit 1 DBG_STOP: Debug Stop mode
Bit 0 DBG_SLEEP: Debug Sleep mode
46.16.4 Debug MCU APB1 freeze register1(DBGMCU_APB1FZR1)
Address: 0xE004 2008
Power on reset (POR): 0x0000 0000
System reset: not affected
Access: Only 32-bit access are supported.
31 30
DBG_LPTIM1_ DBG_I2C3_
STOP STOP
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15 14
Res. Res.
2062/2083
0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
From software point of view, exiting from Standby is identical than fetching reset vector
(except a few status bit indicated that the MCU is resuming from Standby)
1: (FCLK=On, HCLK=On) In this case, the digital part is not unpowered and FCLK and
HCLK are provided by the internal RC oscillator which remains active. In addition, the MCU
generate a system reset during Standby mode so that exiting from Standby is identical than
fetching from reset.
0: (FCLK=Off, HCLK=Off) In STOP mode, the clock controller disables all clocks (including
HCLK and FCLK). When exiting from STOP mode, the clock configuration is identical to the
one after RESET (CPU clocked by the 8 MHz internal RC oscillator (HSI16)). Consequently,
the software must reprogram the clock controller to enable the PLL, the Xtal, etc.
1: (FCLK=On, HCLK=On) In this case, when entering STOP mode, FCLK and HCLK are
provided by the internal RC oscillator which remains active in STOP mode. When exiting
STOP mode, the software must reprogram the clock controller to enable the PLL, the Xtal,
etc. (in the same way it would do in case of DBG_STOP=0)
0: (FCLK=On, HCLK=Off) In Sleep mode, FCLK is clocked by the system clock as
previously configured by the software while HCLK is disabled.
In Sleep mode, the clock controller configuration is not reset and remains in the previously
programmed state. Consequently, when exiting from Sleep mode, the software does not
need to reconfigure the clock controller.
1: (FCLK=On, HCLK=On) In this case, when entering Sleep mode, HCLK is fed by the same
clock that is provided to FCLK (system clock as previously configured by the software).
29 28 27 26
Res. Res. Res. Res.
13 12 11 10
DBG_ DBG_ DBG_
Res. IWDG_ WWDG RTC_
STOP _STOP STOP
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25 24 23
DBG_
Res. Res. Res. I2C2_
STOP
9 8 7
Res. Res. Res.
RM0440 Rev 1
22 21 20 19
DBG_
I2C1_ Res. Res.
STOP
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6 5 4 3
DBG_ DBG_ DBG_
DBG_
TIM7 TIM6 TIM5
Res. TIM4_
_STO _STO _STO
STOP
P P P
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RM0440
18 17 16
Res. Res. Res.
2 1 0
DBG_ DBG_
TIM3_ TIM2_
STOP STOP
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