User Manuals: Renesas H8S/2612 F-ZTAT Microcontroller

Manuals and User Guides for Renesas H8S/2612 F-ZTAT Microcontroller. We have 1 Renesas H8S/2612 F-ZTAT Microcontroller manual available for free PDF download: Hardware Manual

Renesas H8S/2612 F-ZTAT Hardware Manual (609 pages)

16-Bit Single-Chip Microcomputer

Brand: Renesas | Category: Computer Hardware | Size: 3 MB

Table of Contents
11
Section 1 Overview

37
Section 2 CPU

49
Section 3 MCU Operating Modes

87
Section 4 Exception Handling

93
Section 5 Interrupt Controller

103
Section 6 PC Break Controller (PBC)

125
Section 7 Bus Controller

133
- Basic Timing
  133
- Bus Arbitration
  137
  - Order of Priority of the Bus Masters
    137
  - Bus Transfer Timing
    137
Section 8 Data Transfer Controller (DTC)

139
- Features
  139
- Figure 8.1 Block Diagram of DTC
  140
- Register Configuration
  141
  - DTC Mode Register a (MRA)
    142
  - DTC Mode Register B (MRB)
    143
  - DTC Source Address Register (SAR)
    143
  - DTC Destination Address Register (DAR)
    143
  - DTC Transfer Count Register a (CRA)
    143
  - DTC Transfer Count Register B (CRB)
    144
  - DTC Enable Registers (DTCER)
    144
  - DTC Vector Register (DTVECR)
    145
- Activation Sources
  145
- Location of Register Information and DTC Vector Table
  146
- Figure 8.2 Block Diagram of DTC Activation Source Control
  146
- Figure 8.3 Correspondence between DTC Vector Address and Register Information
  147
- Table 8.1 Interrupt Sources, DTC Vector Addresses, and Corresponding Dtces
  148
- Operation
  150
- Procedures for Using DTC
  159
  - Activation by Interrupt
    159
  - Activation by Software
    159
- Examples of Use of the DTC
  159
  - Normal Mode
    159
  - Chain Transfer
    160
  - Software Activation
    161
- Usage Notes
  162
  - Module Stop Mode Setting
    162
  - On-Chip RAM
    162
  - DTCE Bit Setting
    162
Section 9 I/O Ports

163
- Table 9.1 Port Functions
  164
- Port 1
  166
  - Port 1 Data Direction Register (P1DDR)
    166
  - Port 1 Data Register (P1DR)
    167
  - Port 1 Register (PORT1)
    167
  - Pin Functions
    168
  - Table 9.2 P17 Pin Function
    168
  - Table 9.3 P16 Pin Function
    168
  - Table 9.4 P15 Pin Function
    169
  - Table 9.5 P14 Pin Function
    169
  - Table 9.6 P13 Pin Function
    169
  - Table 9.7 P12 Pin Function
    170
  - Table 9.8 P11 Pin Function
    170
  - Table 9.9 P10 Pin Function
    170
- Port 4
  171
  - Port 4 Register (PORT4)
    171
- Port 9
  172
  - Port 9 Register (PORT9)
    172
- Port a
  173
  - Port a Data Direction Register (PADDR)
    173
  - Port a Data Register (PADR)
    174
  - Port a Register (PORTA)
    174
  - Port a Pull-Up MOS Control Register (PAPCR)
    175
  - Port a Open-Drain Control Register (PAODR)
    175
  - Pin Functions
    176
  - Table 9.10 PA3 Pin Function
    176
  - Table 9.11 PA2 Pin Function
    176
  - Table 9.12 PA1 Pin Function
    176
  - Table 9.13 PA0 Pin Function
    176
- Port B
  177
  - Port B Data Direction Register (PBDDR)
    177
  - Port B Data Register (PBDR)
    178
  - Port B Register (PORTB)
    178
  - Port B Pull-Up MOS Control Register (PBPCR)
    179
  - Port B Open-Drain Control Register (PBODR)
    179
  - Pin Functions
    180
  - Table 9.14 PB7 Pin Function
    180
  - Table 9.15 PB6 Pin Function
    180
  - Table 9.16 PB5 Pin Function
    181
  - Table 9.17 PB4 Pin Function
    181
  - Table 9.18 PB3 Pin Function
    181
  - Table 9.19 PB2 Pin Function
    182
  - Table 9.20 PB1 Pin Function
    182
  - Table 9.21 PB0 Pin Function
    182
- Port C
  183
  - Port C Data Direction Register (PCDDR)
    183
  - Port C Data Register (PCDR)
    184
  - Port C Register (PORTC)
    184
  - Port C Pull-Up MOS Control Register (PCPCR)
    185
  - Port C Open-Drain Control Register (PCODR)
    185
  - Pin Functions
    186
- Port D
  188
- Port F
  191
  - Port F Data Direction Register (PFDDR)
    191
  - Port F Data Register (PFDR)
    192
  - Port F Register (PORTF)
    192
  - Pin Functions
    193
Section 10 16-Bit Timer Pulse Unit (TPU)

195
Section 11 Motor Management Timer (MMT)

281
- Features
  281
- Figure 11.1 Block Diagram of MMT
  282
- Input/Output Pins
  283
- Register Descriptions
  283
  - Table 11.1 Pin Configuration
    283
  - Timer Mode Register (TMDR)
    284
  - Timer Control Register (TCNR)
    285
  - Timer Counter (TCNT)
    286
  - Timer Status Register (TSR)
    286
  - Timer Buffer Registers (TBR)
    287
  - Timer Dead Time Counters (TDCNT)
    287
  - Timer Dead Time Data Register (TDDR)
    287
  - Timer General Registers (TGR)
    287
  - Timer Period Buffer Register (TPBR)
    287
  - Timer Period Data Register (TPDR)
    287
  - MMT Pin Control Register (MMTPC)
    288
- Operation
  289
- Interrupts
  299
- Table 11.3 MMT Interrupt Sources
  299
- Operation Timing
  300
- Usage Notes
  306
- Port Output Enable (POE)
  310
  - Features
    310
  - Figure 11.21 Block Diagram of POE
    310
  - Input/Output Pins
    311
  - Register Descriptions
    311
  - Table 11.4 Pin Configuration
    311
  - Operation
    315
  - Figure 11.22 Low Level Detection Operation
    315
Section 12 Programmable Pulse Generator (PPG)

317
Section 13 Watchdog Timer

339
- Features
  339
- Register Descriptions
  340
- Operation
  344
  - Watchdog Timer Mode
    344
  - Interval Timer Mode
    344
- Interrupts
  345
- Usage Notes
  345
Section 14 Serial Communication Interface (SCI)

349
Section 15 Controller Area Network (HCAN)

421
- Features
  421
- Figure 15.1 HCAN Block Diagram
  422
- Input/Output Pins
  423
- Register Descriptions
  423
  - Table 15.1 HCAN Pins
    423
  - Master Control Register (MCR)
    424
  - General Status Register (GSR)
    425
  - Bit Configuration Register (BCR)
    427
  - Mailbox Configuration Register (MBCR)
    429
  - Transmit Wait Register (TXPR)
    430
  - Transmit Wait Cancel Register (TXCR)
    431
  - Transmit Acknowledge Register (TXACK)
    432
  - Abort Acknowledge Register (ABACK)
    433
  - Receive Complete Register (RXPR)
    434
  - Remote Request Register (RFPR)
    435
  - Interrupt Register (IRR)
    436
  - Mailbox Interrupt Mask Register (MBIMR)
    440
  - Interrupt Mask Register (IMR)
    441
  - Receive Error Counter (REC)
    442
  - Transmit Error Counter (TEC)
    442
  - Unread Message Status Register (UMSR)
    443
  - Local Acceptance Filter Masks (LAFML, LAFMH)
    444
  - Figure 15.2 Message Control Register Configuration
    447
  - Figure 15.3 Standard Format
    447
  - Figure 15.4 Extended Format
    447
  - Message Control (MC0 to MC15)
    447
  - Figure 15.5 Message Data Configuration
    449
  - Message Data (MD0 to MD15)
    449
  - HCAN Monitor Register (HCANMON)
    450
- Operation
  451
- Interrupts
  467
- Table 15.4 HCAN Interrupt Sources
  467
- DTC Interface
  468
- Figure 15.15 DTC Transfer Flowchart
  468
- CAN Bus Interface
  469
- Usage Notes
  469
  - Module Stop Mode Setting
    469
  - Reset
    469
  - Figure 15.16 High-Speed Interface Using PCA82C250
    469
  - HCAN Sleep Mode
    470
  - Interrupts
    470
  - Error Counters
    470
  - Register Access
    470
  - HCAN Medium-Speed Mode
    470
  - Register Hold in Standby Modes
    470
  - Usage of Bit Manipulation Instructions
    470
  - 15.8.10 HCAN TXCR Operation
    471
Section 16 A/D Converter

473
- Features
  473
- Figure 16.1 Block Diagram of A/D Converter
  474
- Input/Output Pins
  475
- Table 16.1 Pin Configuration
  475
- Register Description
  476
- Operation
  480
  - Single Mode
    480
  - Scan Mode
    480
  - Input Sampling and A/D Conversion Time
    481
  - Figure 16.2 A/D Conversion Timing
    481
  - Table 16.3 A/D Conversion Time (Single Mode)
    482
  - Table 16.4 A/D Conversion Time (Scan Mode)
    482
  - External Trigger Input Timing
    483
- Interrupts
  483
- Figure 16.3 External Trigger Input Timing
  483
- Table 16.5 A/D Converter Interrupt Source
  483
- A/D Conversion Precision Definitions
  484
- Figure 16.4 A/D Conversion Precision Definitions
  485
- Figure 16.5 A/D Conversion Precision Definitions
  485
- Usage Notes
  486
Section 17 RAM

489
Section 18 ROM

491
Section 19 Clock Pulse Generator

517
Section 20 Power-Down Modes

527
Section 21 Electrical Characteristics

543
- Absolute Maximum Ratings
  543
- Table 21.1 Absolute Maximum Ratings
  543
- DC Characteristics
  544
- Table 21.2 DC Characteristics
  544
- AC Characteristics
  547
- A/D Conversion Characteristics
  556
- Table 21.7 A/D Conversion Characteristics
  556
- Flash Memory Characteristics
  557
- Table 21.8 Flash Memory Characteristics
  557
Appendix

559
- On-Chip I/O Register
  559
  - Register Addresses
    559
  - Register Bits
    575
  - Register States in each Operating Mode
    589
- I/O Port States in each Pin State
  600
- Product Code Lineup
  601
- Package Dimensions
  602
Index

603

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User Manuals: Renesas H8S/2612 F-ZTAT Microcontroller

Renesas H8S/2612 F-ZTAT Hardware Manual (609 pages)

Table of Contents

Section 1 Overview

Section 2 CPU

Section 3 MCU Operating Modes

Section 4 Exception Handling

Section 5 Interrupt Controller

Section 6 PC Break Controller (PBC)

Section 7 Bus Controller

Section 8 Data Transfer Controller (DTC)

Section 9 I/O Ports

Section 10 16-Bit Timer Pulse Unit (TPU)

Section 11 Motor Management Timer (MMT)

Section 12 Programmable Pulse Generator (PPG)

Section 13 Watchdog Timer

Section 14 Serial Communication Interface (SCI)

Section 15 Controller Area Network (HCAN)

Section 16 A/D Converter

Section 17 RAM

Section 18 ROM

Section 19 Clock Pulse Generator

Section 20 Power-Down Modes

Section 21 Electrical Characteristics

Appendix

Index

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