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16.1 Overview
This LSI has a built-in clock pulse generator (CPG) that generates the system clock (ø) and other
internal clock signals (ø/2 to ø/4096). After duty adjustment, a frequency divider divides the clock
frequency to generate the system clock (ø). The system clock is output at the ø pin*
as a master clock to prescalers that supply clock signals to the on-chip supporting modules.
Frequency division ratios of 1/1, 1/2, 1/4, and 1/8 can be selected for the frequency divider by
settings in a division control register (DIVCR). Power consumption in the chip is reduced in
almost direct proportion to the frequency division ratio*
Notes: 1. Usage of the ø pin differs depending on the chip operating mode and the PSTOP bit
setting in the module standby control register (MSTCR). For details, see section 17.7,
System Clock Output Disabling Function.
2. The division ratio of the frequency divider can be changed dynamically during
operation. The clock output at the ø pin also changes when the division ratio is
changed. The frequency output at the ø pin is shown below.
ø = EXTAL × n
Section 16 Clock Pulse Generator
EXTAL: Frequency of crystal resonator or external clock signal
n:
Frequency division ratio (n = 1/1, 1/2, 1/4, or 1/8)
2
.
1
and furnished
491
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