Control Signal Timing - Hitachi SH7709S Hardware Manual

23.3.2

Control Signal Timing

Table 23.6 Control Signal Timing
(Vcc = 3.3 ± 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C)
Item
RESETP pulse width
RESETP setup time
*1
RESETP hold time
RESETM pulse width
RESETM setup time
RESETM hold time
BREQ setup time
BREQ hold time
1
NMI setup time *
NMI hold time
IRQ5–IRQ0 setup time *
IRQ5–IRQ0 hold time
IRQOUT delay time
BACK delay time
STATUS1, STATUS0 delay time
Bus tri-state delay time 1
Bus tri-state delay time 2
Bus buffer-on time 1
Bus buffer-on time 2
Notes: *1 RESETP, NMI, and IRQ5 to IRQ0 are asynchronous. Changes are detected at the clock
fall when the setup shown is used. When the setup cannot be used, detection can be
delayed until the next clock falls.
*2 The upper limit of the external bus clock is 66 MHz.
*3 In the standby mode, t
= t (10 ms) when XTAL oscillation is off. In the sleep mode, t
OSC2
When the clock multiplication ratio is changed, t
*4 In the standby mode, t
kept low until STATUS (0-1) changes to reset (HH). When the clock multiplication ratio
is changed, RESETM must be kept low until STATUS (0-1) changes to reset (HH).
Symbol
t
RESPW
t
RESPS
t
RESPH
t
RESMW
t
RESMS
t
RESMH
t
BREQS
t
BREQH
t
NMIS
t
NMIH
1
t
IRQS
t
IRQH
t
IRQOD
t
BACKD
t
STD
t
BOFF1
t
BOFF2
t
BON1
t
BON2
= t (100 µs) when XTAL oscillation is continued and t
RESPW OSC1
(10 ms). In the sleep mode, RESETM must be
= t
RESMW OSC2
2
to 66*
Min Max Unit
3
20 * — tcyc
20 — ns
4 — ns
4
20 * — tcyc
6 — ns
34 — ns
6 — ns
4 — ns
10 — ns
4 — ns
10 — ns
4 — ns
— 10 ns
— 10 ns
— 10 ns
0 15 ns
0 15 ns
0 15 ns
0 15 ns
RESPW
= t (100 µs).
RESPW PLL1
Figure
23.11,
23.12
23.14
23.12
23.13
23.14,
23.15
RESPW
= t (100 µs).
PLL1
679