Section 18 Clock Pulse Generator; Overview; Block Diagram - Hitachi H8/3006 Hardware Manual

18.1

Overview

The H8/3006 and H8/3007 have a built-in clock pulse generator (CPG) that generates the system
clock (φ) and other internal clock signals (φ/2 to φ/4096). After duty adjustment, a frequency
divider divides the clock frequency to generate the system clock (φ). The system clock is output at
the φ pin*
1
and furnished as a master clock to prescalers that supply clock signals to the on-chip
supporting modules. Frequency division ratios of 1/1, 1/2, 1/4, and 1/8 can be selected for the
frequency divider by settings in a division control register (DIVCR)*
chip is reduced in almost direct proportion to the frequency division ratio.
Notes: 1. Usage of the φ pin differs depending on the chip operating mode and the PSTOP bit
setting in the module standby control register (MSTCR). For details, see section 19.7,
System Clock Output Disabling Function.
2. The division ratio of the frequency divider can be changed dynamically during
operation. The clock output at the φ pin also changes when the division ratio is
changed. The frequency output at the φ pin is shown below.
φ = EXTAL × n
where, EXTAL:Frequency of crystal resonator or external clock signal
n:
18.1.1

Block Diagram

Figure 18.1 shows a block diagram of the clock pulse generator.
XTAL
EXTAL
Figure 18.1 Block Diagram of Clock Pulse Generator

Section 18 Clock Pulse Generator

Frequency division ratio (n = 1/1, 1/2, 1/4, or 1/8)
Oscillator
adjustment
Duty
Frequency
divider
circuit
Division
control
register
Data bus
2
. Power consumption in the
CPG
Prescalers
φ φ/2 to φ/4096
549