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Bit
0
1
Field
Reset
R/W
Addr
Bit
16
17
18
Field
Reset
R/W
Addr
Table 10-10 describes MDR Þelds.
Bits
Name
0Ð31
MD
Memory data. The data to be read or written into the RAM array when a
supplied to the UPM.
10.3.7 Memory Address Register (MAR)
The memory address register (MAR) is shown in Figure 10-13.
Bit
0
1
2
Field
Reset
R/W
Addr
Bit
16
17
18
Field
Reset
R/W
Addr
Figure 10-13. Memory Address Register (MAR)
MOTOROLA
2
3
4
5
6
0000_0000_0000_0000
19
20
21
22
0000_0000_0000_0000
Figure 10-12. Memory Data Register (MDR)
Table 10-10. MDR Field Descriptions
3
4
5
6
0000_0000_0000_0000
19
20
21
22
0000_0000_0000_0000
Chapter 10. Memory Controller
7
8
9
10
11
MD
R/W
0x10188
23
24
25
26
27
MD
R/W
0x1018A
Description
7
8
9
10
A
R/W
0x10168
23
24
25
26
A
R/W
0x10116A
Part III. The Hardware Interface
12
13
14
28
29
30
or
command is
WRITE
READ
11
12
13
14
27
28
29
30
15
31
15
31
10-29
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