Exception Recognition And Priorities - Motorola MPC750 User Manual

Table 4-2. Exceptions and Conditions (Continued)
Exception Type
Vector Offset
Causing Conditions
(hex)
Reserved 0150D-016FF
-
Thermal 01700 Thermal management is enabled, junction temperature exceeds the threshold
management interrupt specified in THRM 1 or THRM2, and MSR[EE]
=
1 (MPC750-specific)
Reserved
0180o-02FFF
-
4.2 Exception Recognition and Priorities
Exceptions are roughly prioritized by exception class, as follows:
1. Nonmaskable, asynchronous exceptions have priority over all other exceptions-
system reset and machine check exceptions (although the machine check exception
condition can be disabled so the condition causes the processor to go directly into
the checkstop state). These exceptions cannot be delayed and do not wait for
completion of any precise exception handling.
2. Synchronous, precise exceptions are caused by instructions and are taken in strict
program order.
3. Imprecise exceptions (imprecise mode floating-point enabled exceptions) are
caused by instructions and they are delayed until higher priority exceptions are
taken. Note that the MPC750 does not implement an exception of this type.
4. Maskable asynchronous exceptions (external, decrementer, thermal management,
system management, performance monitor, and interrupt exceptions) are delayed
until higher priority exceptions are taken.
The following list of exception categories describes how the MPC750 handles exceptions
up to the point of signaling the appropriate interrupt to occur. Note that a recoverable state
is reached if the completed store queue is empty (drained, not canceled) and any instruction
that is next in program order and has been signaled to complete has completed. If
MSR[RI]
=
0, the MPC750 is in a nonrecoverable state. Also, instruction completion is
defined as updating all architectural registers associated with that instruction, and then
removing that instruction from the completion buffer.
4-4
• Exceptions caused by asynchronous events (interrupts). These exceptions are further
distinguished by whether they are maskable and recoverable.
- Asynchronous, nonmaskable, nonrecoverable
System reset for assertion of HRESET -Has highest priority and is taken
immediately regardless of other pending exceptions or recoverability. (Includes
power-on reset)
MPC750 RISC Microprocessor User's Manual